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Design Rule Evaluation Framework Using Automatic Cell Layout Generator for Design Technology Co-Optimization
by
Jo, Kyeongrok
,
Ahn, Seyong
,
Do, Jungho
,
Song, Taejoong
,
Kim, Taewhan
,
Choi, Kyumyung
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IEEE transactions on very large scale integration (VLSI) systems
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Synthesis and Utilization of Standard Cells Amenable to Gear Ratio of Gate-Metal Pitches for Improving Pin Accessibility
by
Jeong, Jooyeon
,
Chung, Sehyeon
,
Jo, Kyeongrok
,
Kim, Taewhan
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Optimal Transistor Placement Combined with Global In-cell Routing in Standard Cell Layout Synthesis
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Jo, Kyeongrok
,
Kim, Taewhan
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Boosting Pin Accessibility Through Cell Layout Topology Diversification
by
Kim, Suwan
,
Jo, Kyeongrok
,
Kim, Taewhan
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Cohesive techniques for cell layout optimization supporting 2D metal-1 routing completion
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Jo, Kyeongrok
,
Ahn, Seyong
,
Kim, Taewhan
,
Choi, Kyumyung
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