Search Results - Kadayinti, Naveen

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  1. 1
    Reduced graphene oxide based ultrasensitive resistive sensor for detection of CA125

    Reduced graphene oxide based ultrasensitive resistive sensor for detection of CA125 by Konthoujam, Bolivia, Bhandari, Nikita, Kamal, Miriyala Pranay, Srinivas, P. Nitin, Thati, Bhanoday, Bondugula, Pranav, Reddy, Purushotham, Antaratani, Ramalingappa C., Kadayinti, Naveen, Shukla, Sudhanshu, Ghosh, Ruma

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  2. 2
    CMOS-MEMS Accelerometer With Stepped Suspended Gate FET Array: Design & Analysis

    CMOS-MEMS Accelerometer With Stepped Suspended Gate FET Array: Design & Analysis by Martha, Pramod, Kadayinti, Naveen, Seena, V.

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  3. 3
    A CMOS-MEMS Accelerometer With U-Channel Suspended Gate SOI FET

    A CMOS-MEMS Accelerometer With U-Channel Suspended Gate SOI FET by Martha, Pramod, Kadayinti, Naveen, Seena, V.

    Published in IEEE sensors journal
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  4. 4
    A Closed-Loop In-Plane Movable Suspended Gate FET (CLIP-SGFET) Sensor With a Dynamically Reconfigurable Charge Pump

    A Closed-Loop In-Plane Movable Suspended Gate FET (CLIP-SGFET) Sensor With a Dynamically Reconfigurable Charge Pump by Martha, Pramod, Ganga, K. M., Sebastian, Anju, Seena, V., Kadayinti, Naveen

    Published in IEEE sensors journal
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  5. 5
    A True Time Delay Element using Cascaded Variable Bandwidth All Pass Filters

    A True Time Delay Element using Cascaded Variable Bandwidth All Pass Filters by Marinaik, Mayur S., Maheshwarappa, Ganga K., Kadayinti, Naveen

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  6. 6
    TRNG Based on Multiple Entropy Sources Using CTDSM

    TRNG Based on Multiple Entropy Sources Using CTDSM by Pandey, Apurv, Kadayinti, Naveen

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  7. 7
    Effect of jitter on the settling time of mesochronous clock retiming circuits

    Effect of jitter on the settling time of mesochronous clock retiming circuits by Kadayinti, Naveen, Budkuley, Amitalok J., Baghini, Maryam S., Sharma, Dinesh K.

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  8. 8
    A Clock Retiming Circuit for Repeaterless Low Swing On-Chip Interconnects

    A Clock Retiming Circuit for Repeaterless Low Swing On-Chip Interconnects by Kadayinti, Naveen, Baghini, Maryam Shojaei, Sharma, Dinesh K.

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  9. 9
    Clock Skew Measurement Using an All-Digital Sigma-Delta Time to Digital Converter

    Clock Skew Measurement Using an All-Digital Sigma-Delta Time to Digital Converter by Shirwaikar, Mahadev Govind, Kadayinti, Naveen, Sharma, Dinesh K.

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  10. 10
    Sense amplifier comparator with offset correction for decision feedback equalization based receivers

    Sense amplifier comparator with offset correction for decision feedback equalization based receivers by Kadayinti, Naveen, Sharma, Dinesh K.

    Published in Microelectronics
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  11. 11
    Measurements of the effect of jitter on the performance of clock retiming circuits for on-chip interconnects

    Measurements of the effect of jitter on the performance of clock retiming circuits for on-chip interconnects by Kadayinti, Naveen, Shojaei Baghini, Maryam, Sharma, Dinesh K.

    Published in Microelectronics
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  12. 12
    A Technique for Modeling and Simulating Transistor Based MEMS Sensors

    A Technique for Modeling and Simulating Transistor Based MEMS Sensors by Martha, Pramod, Sebastian, Anju, Seena, V., Kadayinti, Naveen

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  13. 13
    Sense Amplifier Comparator with Offset Correction for Decision Feedback Equalization based Receivers

    Sense Amplifier Comparator with Offset Correction for Decision Feedback Equalization based Receivers by Kadayinti, Naveen, Sharma, Dinesh

    Published in arXiv.org
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  14. 14
    Effect of Jitter on the Settling Time of Mesochronous Clock Retiming Circuits

    Effect of Jitter on the Settling Time of Mesochronous Clock Retiming Circuits by Kadayinti, Naveen, Budkuley, Amitalok J, Baghini, Maryam S, Sharma, Dinesh K

    Published in arXiv.org
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  15. 15
    Impact of Sampler Offset on Jitter Transfer in Clock and Data Recovery Circuits

    Impact of Sampler Offset on Jitter Transfer in Clock and Data Recovery Circuits by Kadayinti, Naveen, Maryam Shojaei Baghini, Sharma, Dinesh K

    Published in arXiv.org
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  16. 16
    Testable Design of Repeaterless Low Swing On-Chip Interconnect

    Testable Design of Repeaterless Low Swing On-Chip Interconnect by Kadayinti, Naveen, Sharma, Dinesh K

    Published in arXiv.org
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  17. 17
    A Clock Synchronizer for Repeaterless Low Swing On-Chip Links

    A Clock Synchronizer for Repeaterless Low Swing On-Chip Links by Kadayinti, Naveen, Maryam Shojaei Baghini, Sharma, Dinesh K

    Published in arXiv.org
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