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A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS
by
Kimura, Hiroshi
,
Aziz, Pervez M.
,
Tai Jing
,
Sinha, Ashutosh
,
Kotagiri, Shiva Prasad
,
Narayan, Ram
,
Hairong Gao
,
Ping Jing
,
Hom, Gary
,
Anshi Liang
,
Zhang, Eric
,
Kadkol, Aniket
,
Kothari, Ruchi
,
Chan, Gordon
,
Yehui Sun
,
Ge, Benjamin
,
Zeng, Jason
,
Ling, Kathy
,
Wang, Michael C.
,
Malipatil, Amaresh
,
Lijun Li
,
Abel, Christopher
,
Zhong, Freeman
Published in
IEEE journal of solid-state circuits
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2.1 28Gb/s 560mW multi-standard SerDes with single-stage analog front-end and 14-tap decision-feedback equalizer in 28nm CMOS
by
Kimura, Hiroshi
,
Aziz, Pervez
,
Tai Jing
,
Sinha, Ashutosh
,
Narayan, Ram
,
Hairong Gao
,
Ping Jing
,
Hom, Gary
,
Liang, Anshi
,
Zhang, Eric
,
Kadkol, Aniket
,
Kothari, Ruchi
,
Chan, Gordon
,
Yehui Sun
,
Ge, Benjamin
,
Zeng, Jason
,
Ling, Kathy
,
Wang, Michael
,
Malipatil, Amaresh
,
Kotagiri, Shiva
,
Lijun Li
,
Abel, Chris
,
Zhong, Freeman
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Ieee Journal Of Solid-State Circuits
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Clocks
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Decision Feedback Equalizers
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28 Gb/S Serdes
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Active Inductor
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Active Inductors
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Bandwidth
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Couplings
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Engineering
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Group Delay Adaptation
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Inductors
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Latches
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Phase Locked Loops
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Power Demand
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Science & Technology
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System-On-Chip
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Tia-Based Analog Front End
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Transceivers
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Unrolled Dfe
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