Search Results - Kai-Yap Toh

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  1. 1
    A 23-ps/2.1-mW ECL gate with an AC-coupled active pull-down emitter-follower stage

    A 23-ps/2.1-mW ECL gate with an AC-coupled active pull-down emitter-follower stage by Kai-Yap Toh, Ching-Te Chuang, Tze-Chiang Chen, Warnock, J.D.

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  2. 2
    An engineering model for short-channel MOS devices

    An engineering model for short-channel MOS devices by Toh, K.-y., Ko, P.-K., Meyer, R.G.

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  3. 3
    The design and optimization of high-performance, double-poly self-aligned p-n-p technology

    The design and optimization of high-performance, double-poly self-aligned p-n-p technology by Lu, P.-F., Warnock, J.D., Cressler, J.D., Jenkins, K.A., Toh, K.-Y.

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  4. 4
    Wide-band, low-noise, matched-impedance amplifiers in submicrometer MOS technology

    Wide-band, low-noise, matched-impedance amplifiers in submicrometer MOS technology by Toh, K.-Y., Meyer, R.G., Soo, D.C., Chin, G.M., Voshchenkov, A.M.

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