Search Results - Kalenteridis, V

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  1. 1
    A CMOS linear-in-dB VGA and AGC loop for telecommunication applications

    A CMOS linear-in-dB VGA and AGC loop for telecommunication applications by Kalenteridis, V., Mountrichas, L., Vlassis, S., Siskos, S.

    Published in Microelectronics
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  2. 2
    A complete platform and toolset for system implementation on fine-grain reconfigurable hardware

    A complete platform and toolset for system implementation on fine-grain reconfigurable hardware by Kalenteridis, V., Pournara, H., Siozos, K., Tatas, K., Vassiliadis, N., Pappas, I., Koutroumpezis, G., Nikolaidis, S., Siskos, S., Soudris, D.J., Thanailakis, A.

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  3. 3
    A study of different types of current mirrors using polysilicon TFTs

    A study of different types of current mirrors using polysilicon TFTs by Pappas, I, Nalpantidis, L, Kalenteridis, V, Siskos, S, Dimitriadis, C A, Hatzopoulos, A A

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  4. 4
    Fine-grain reconfigurable platform: FPGA hardware design and software toolset development

    Fine-grain reconfigurable platform: FPGA hardware design and software toolset development by Pappas, I, Kalenteridis, V, Vassiliadis, N, Pournara, H, Siozios, K, Koutroumpezis, G, Tatas, K, Nikolaidis, S, Siskos, S, Soudris, D J, Thanailakis, A

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  5. 5
    A complete over-current/short-circuit protection system for Low-Drop Out regulators

    A complete over-current/short-circuit protection system for Low-Drop Out regulators by Pappas, I., Kalenteridis, V., Siskos, S., Vlassis, S.

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  6. 6
    A CMOS linear-in-dB VGA based on exponential current generator

    A CMOS linear-in-dB VGA based on exponential current generator by Kalenteridis, V., Vlassis, S., Siskos, S.

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  7. 7
    AGC loop implementation using temperature compensated CMOS linear-in-dB VGA

    AGC loop implementation using temperature compensated CMOS linear-in-dB VGA by Kalenteridis, V., Siskos, S., Vlassis, S.

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  8. 8
    A threshold voltage variation cancellation technique for analogue peripheral circuits of a display array using poly-Si TFTs

    A threshold voltage variation cancellation technique for analogue peripheral circuits of a display array using poly-Si TFTs by Pappas, I., Nalpantidis, L., Kalenteridis, V., Siskos, S., Hatzopoulos, A.A., Dimitriadis, C.A.

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  9. 9
    A 60-GHz quadrature PLL in 90nm CMOS

    A 60-GHz quadrature PLL in 90nm CMOS by Plessas, F., Panagiotopoulos, V., Kalenteridis, V., Souliotis, G., Liakou, F., Koutsomitsos, S., Siskos, S., Birbas, A.

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  10. 10
    An integrated FPGA design framework: custom designed FPGA platform and application mapping toolset development

    An integrated FPGA design framework: custom designed FPGA platform and application mapping toolset development by Kalenteridis, V., Pournara, H., Siozios, K., Tatas, K., Koytroympezis, G., Pappas, I., Nikolaidis, S., Siskos, S., Soudris, D.J., Thanailakis, A.

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  11. 11
    AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow

    AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow by Soudris, D., Nikolaidis, S., Siskos, S., Tatas, K., Siozios, K., Koutroumpezis, G., Vasiliadis, N., Kalenteridis, V., Pournara, H., Pappas, I., Thanailakis, A.

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