Search Results - Kanasugi, Akinori

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  1. 1
    An integrated machine code monitor for a RISC-V processor on an FPGA

    An integrated machine code monitor for a RISC-V processor on an FPGA by Kaneko, Hiroaki, Kanasugi, Akinori

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  2. 2
    A design of EPIC type processor based on MIPS architecture

    A design of EPIC type processor based on MIPS architecture by Hayashi, Takahito, Kanasugi, Akinori

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  3. 3
    Accuracy improvement of genetic algorithm for obtaining floating-point solution

    Accuracy improvement of genetic algorithm for obtaining floating-point solution by Nishijima, Kengo, Kanasugi, Akinori, Ando, Ki

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  4. 4
    Genetic algorithm with dynamic variable number of individuals and accuracy

    Genetic algorithm with dynamic variable number of individuals and accuracy by Tsukahara, Akihiko, Kanasugi, Akinori

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  5. 5
    A novel architecture of dynamically reconfigurable fused multiply–adder for digital signal processing

    A novel architecture of dynamically reconfigurable fused multiply–adder for digital signal processing by Tsukahara, Akihiko, Kanasugi, Akinori

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  6. 6
    Hardware implementation of evolutionary algorithms using dynamic reconfiguration technology

    Hardware implementation of evolutionary algorithms using dynamic reconfiguration technology by Kanasugi, Akinori, Tsukahara, Akihiko, Ando, Ki

    Published in Natural computing
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  7. 7
    Generator of dynamically reconfigurable processor

    Generator of dynamically reconfigurable processor by Sega, Takahiko, Kanasugi, Akinori, Ando, Ki

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  8. 8
    A novel coding method for genetic algorithms based on redundant binary numbers

    A novel coding method for genetic algorithms based on redundant binary numbers by Murayama, Akira, Kanasugi, Akinori

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  9. 9
    A dynamically reconfigurable processor for H.264/AVC image prediction

    A dynamically reconfigurable processor for H.264/AVC image prediction by Hayakawa, Yuki, Kanasugi, Akinori

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  10. 10
    Analysis of Plant Bioelectric Potential Response to Illumination by Curve Fitting

    Analysis of Plant Bioelectric Potential Response to Illumination by Curve Fitting by Ando, Ki, Hasegawa, Yuki, Uchida, Hidekazu, Kanasugi, Akinori

    Published in Sensors and materials
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  11. 11
    Position detection method for microwell chip on microscope stage by photon multiplier tube

    Position detection method for microwell chip on microscope stage by photon multiplier tube by Ando, Ki, Uchida, Hidekazu, Ahmed, Shamim, Nishigaki, Koichi, Takei, Osamu, Kanasugi, Akinori

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  12. 12
    Genetic Algorithm with Dynamic Variable Number of Individuals and Accuracy

    Genetic Algorithm with Dynamic Variable Number of Individuals and Accuracy by Tsukahara, Akihiko, Kanasugi, Akinori

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  13. 13
    A parallel processor for distributed genetic algorithm with redundant binary number

    A parallel processor for distributed genetic algorithm with redundant binary number by Kamimura, T., Kanasugi, A.

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  14. 14
    A Design and Simulation for Dynamically Reconfigurable Systolic Array

    A Design and Simulation for Dynamically Reconfigurable Systolic Array by Ishimura, T., Kanasugi, A.

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  15. 15
    A Processor for Genetic Algorithm Based on Redundant Binary Number

    A Processor for Genetic Algorithm Based on Redundant Binary Number by Aoshima, M., Kanasugi, A.

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  16. 16
    Genetic Algorithm that can Dynamically Change Number of Individuals and Accuracy

    Genetic Algorithm that can Dynamically Change Number of Individuals and Accuracy by Tsukahara, A., Kanasugi, A.

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  17. 17
    A Processor for Genetic Algorithm using Dynamically Reconfigurable Memory

    A Processor for Genetic Algorithm using Dynamically Reconfigurable Memory by Kanasugi, A., Tsukahara, A.

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  18. 18
    A fuzzy processor using Josephson junctions

    A fuzzy processor using Josephson junctions by Morisue, M., Ishii, N., Kanasugi, A.

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  19. 19
    A wafer-scale 170000-gate FFT processor with built-in test circuits

    A wafer-scale 170000-gate FFT processor with built-in test circuits by Yamashita, K., Kanasugi, A., Hijiya, S., Goto, G., Matsumura, N., Shirato, T.

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  20. 20
    A wafer-scale FFT processor featuring a repeatable building block

    A wafer-scale FFT processor featuring a repeatable building block by Yamashita, K., Kanasugi, A., Hijiya, S., Goto, G.

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