Search Results - Katevenis, Manolis G. H.

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  1. 1
    LP-NUCA: Networks-in-Cache for High-Performance Low-Power Embedded Processors

    LP-NUCA: Networks-in-Cache for High-Performance Low-Power Embedded Processors by Gracia, D. S., Dimitrakopoulos, G., Arnal, T. M., Katevenis, M. G. H., Yufera, V. V.

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  2. 2
    Pipelined Heap (Priority Queue) Management for Advanced Scheduling in High-Speed Networks

    Pipelined Heap (Priority Queue) Management for Advanced Scheduling in High-Speed Networks by Ioannou, A., Katevenis, M.G.H.

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  3. 3
    Explicit Communication and Synchronization in SARC

    Explicit Communication and Synchronization in SARC by Katevenis, Manolis G H, Papaefstathiou, V, Kavadias, S, Pnevmatikatos, D, Nikolopoulos, Dimitrios S, Silla, Federico

    Published in IEEE MICRO
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  4. 4
    Efficient Convolutional Neural Network Weight Compression for Space Data Classification on Multi-fpga Platforms

    Efficient Convolutional Neural Network Weight Compression for Space Data Classification on Multi-fpga Platforms by Pitsis, George, Tsagkatakis, Grigorios, Kozanitis, Christos, Kalomoiris, Ioannis, Ioannou, Aggelos, Dollas, Apostolos, Katevenis, Manolis G.H., Tsakalides, Panagiotis

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  5. 5
    Web-conscious storage management for Web proxies

    Web-conscious storage management for Web proxies by Markatos, E.P., Pnevmatikatos, D.N., Flouris, M.D., Katevenis, M.G.H.

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  6. 6
    Wormhole IP over (connectionless) ATM

    Wormhole IP over (connectionless) ATM by Katevenis, M.G.H., Mavroidis, Iakovos, Sapountzis, G., Kalyvianaki, E., Mavroidis, Ioannis, Glykopoulos, G.

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  7. 7
    Modeling Energy-Performance Tradeoffs in ARM big. LITTLE Architectures

    Modeling Energy-Performance Tradeoffs in ARM big. LITTLE Architectures by Vasilakis, Evangelos, Sourdis, Ioannis, Papaefstathiou, Vassilis, Psathakis, Antonis, Katevenis, Manolis G. H.

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  8. 8
    Building an FoC Using Large, Buffered Crossbar Cores

    Building an FoC Using Large, Buffered Crossbar Cores by Simos, D., Papaefstathiou, I., Katevenis, M.G.H.

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  9. 9
    A RISCy approach to VLSI

    A RISCy approach to VLSI by Fitzpatrick, Daniel T., Foderaro, John K., Katevenis, Manolis G. H., Landman, Howard A., Patterson, David A., Peek, James B., Peshkess, Zvi, Séquin, Carlo H., Sherburne, Robert W., Van Dyke, Korbin S.

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  10. 10
    A 32-bit NMOS microprocessor with a large register file

    A 32-bit NMOS microprocessor with a large register file by Sherburne, R.W., Katevenis, M.G.H., Patterson, D.A., Sequin, C.H.

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  11. 11
    Prototyping Efficient Interprocessor Communication Mechanisms

    Prototyping Efficient Interprocessor Communication Mechanisms by Papaefstathiou, V., Pnevmatikatos, D., Marazakis, M., Kalokairinos, G., Ioannou, A., Papamichael, M., Kavadias, S., Mihelogiannakis, G., Katevenis, M.

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