Mitigation of Single-Event Charge Sharing in a Commercial FPGA Architecture by Kelly, Andrew T., Alles, Michael L., Ball, Dennis R., Massengill, Lloyd W., Ramaswamy, S., Haddad, Nadim F., Brown, Ronald D., Fleming, Patrick R., Chan, Ernesto, Ekanayake, Virantha, Kelly, Clinton W., Pelosi, Christopher, McMorrow, Dale, Buchner, Steven P., Warner, Jeffery H., Berg, Melanie D.

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An ultra low-power processor for sensor networks by Ekanayake, Virantha, Kelly IV, Clinton, Manohar, Rajit

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An ultra low-power processor for sensor networks by Ekanayake, Virantha, Clinton Kelly, I V, Manohar, Rajit

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An ultra low-power processor for sensor networks by Ekanayake, Virantha, Kelly, Clinton, Manohar, Rajit

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BitSNAP: dynamic significance compression for a low-energy sensor network asynchronous processor by Ekanayake, V.N., Kelly, C., Manohar, R.

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SNAP: a Sensor-Network Asynchronous Processor by Kelly, C., Ekanayake, V., Manohar, R.

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A radiation hardened reconfigurable FPGA by Ramaswamy, S., Rockett, L., Patel, D., Danziger, S., Manohar, R., Kelly, C.W., Holt, J.L., Ekanayake, V., Elftmann, D.

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An ultra low-power processor for sensor networks by EKANAYAKE, Virantha, KELLY, Clinton IV, MANOHAR, Rajit

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