Search Results - Ken Mai

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  1. 41
    A 1.19GHz 9.52Gsamples/sec Radix-8 FFT Hardware Accelerator in 28nm

    A 1.19GHz 9.52Gsamples/sec Radix-8 FFT Hardware Accelerator in 28nm by Tang, Larry, Chen, Siyuan, Harisrikanth, Keshav, Xu, Guanglin, Franchetti, Franz, Mai, Ken

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  2. 42
    Low-overhead, digital offset compensated, SRAM sense amplifiers

    Low-overhead, digital offset compensated, SRAM sense amplifiers by Bhargava, M., McCartney, M.P., Hoefler, A., Mai, K.

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  3. 43
    Reliability enhancement of bi-stable PUFs in 65nm bulk CMOS

    Reliability enhancement of bi-stable PUFs in 65nm bulk CMOS by Bhargava, Mudit, Cakir, C., Mai, Ken

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  4. 44
    Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS : Small transistors necessitate big changes, in the way digital circuits are modeled and optimized for manufacturability, and new strategies for logic, memory, clocking and power distribution: A Future of Integrated Electronics: Moving Off the Roadmap

    Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS : Small transistors necessitate big changes, in the way digital circuits are modeled and optimized... by CALHOUN, Benton H, YU CAO, XIN LI, KEN MAI, PILEGGI, Lawrence T, RUTENBAR, Rob A, SHEPARD, Kenneth L

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  5. 45
    Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis

    Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis by Yu Cai, Haratsch, E. F., Mutlu, O., Ken Mai

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  6. 46
    Managing wire scaling: a circuit perspective

    Managing wire scaling: a circuit perspective by Ron Ho, Ken Mai, Horowitz, M.

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  7. 47
    Neighbor-cell assisted error correction for MLC NAND flash memories

    Neighbor-cell assisted error correction for MLC NAND flash memories by Cai, Yu, Yalcin, Gulay, Mutlu, Onur, Haratsch, Erich F., Unsal, Osman, Cristal, Adrian, Mai, Ken

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  8. 48
    Attack resistant sense amplifier based PUFs (SA-PUF) with deterministic and controllable reliability of PUF responses

    Attack resistant sense amplifier based PUFs (SA-PUF) with deterministic and controllable reliability of PUF responses by Bhargava, Mudit, Cakir, Cagla, Ken Mai

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  9. 49
    FPGA-Based Solid-State Drive Prototyping Platform

    FPGA-Based Solid-State Drive Prototyping Platform by Yu Cai, Haratsch, E F, McCartney, M, Mai, Ken

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  10. 50
    Threshold voltage distribution in MLC NAND flash memory: characterization, analysis, and modeling

    Threshold voltage distribution in MLC NAND flash memory: characterization, analysis, and modeling by Cai, Yu, Haratsch, Erich F., Mutlu, Onur, Mai, Ken

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  11. 51
    Experimental Characterization, Optimization, and Recovery of Data Retention Errors in MLC NAND Flash Memory

    Experimental Characterization, Optimization, and Recovery of Data Retention Errors in MLC NAND Flash Memory by Cai, Yu, Luo, Yixin, Haratsch, Erich F, Mai, Ken, Ghose, Saugata, Mutlu, Onur

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  12. 52
    Characterizing, Exploiting, and Mitigating Vulnerabilities in MLC NAND Flash Memory Programming

    Characterizing, Exploiting, and Mitigating Vulnerabilities in MLC NAND Flash Memory Programming by Cai, Yu, Ghose, Saugata, Luo, Yixin, Mai, Ken, Mutlu, Onur, Haratsch, Erich F

    Published in arXiv.org
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  13. 53
    Read Disturb Errors in MLC NAND Flash Memory

    Read Disturb Errors in MLC NAND Flash Memory by Cai, Yu, Luo, Yixin, Ghose, Saugata, Haratsch, Erich F, Mai, Ken, Mutlu, Onur

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  14. 54
    Architecture and circuit techniques for a reconfigurable memory block

    Architecture and circuit techniques for a reconfigurable memory block by Mai, K., Ho, R., Alon, E., Dean, L., Younggon Kim, Dinesh, P., Horowitz, M.

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  15. 55
    Extended abstract: A high-performance, low-overhead, power-analysis-resistant, single-rail logic style

    Extended abstract: A high-performance, low-overhead, power-analysis-resistant, single-rail logic style by Menendez, E., Mai, K.

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  16. 56
    Smart Memories: a modular reconfigurable architecture

    Smart Memories: a modular reconfigurable architecture by Mai, Ken, Paaske, Tim, Jayasena, Nuwan, Ho, Ron, Dally, William J., Horowitz, Mark

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  17. 57
    Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding

    Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding by Kim, Jangwoo, Hardavellas, Nikos, Mai, Ken, Falsafi, Babak, Hoe, James

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  18. 58
    PROToFLEX: FPGA-accelerated Hybrid Functional Simulator

    PROToFLEX: FPGA-accelerated Hybrid Functional Simulator by Chung, E.S., Nurvitadhi, E., Hoe, J.C., Falsafi, B., Mai, K.

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  19. 59
    Interconnect scaling implications for CAD

    Interconnect scaling implications for CAD by Ho, R., Mai, K., Kapadia, H., Horowitz, M.

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  20. 60
    Interconnect scaling implications for CAD

    Interconnect scaling implications for CAD by Ho, Ron, Mai, Ken, Kapadia, Hema, Horowitz, Mark

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