Search Results - Ken Mai

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  1. 1
    Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS

    Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS by Calhoun, Benton H., Cao, Yu, Li, Xin, Mai, Ken, Pileggi, Lawrence T., Rutenbar, Rob A., Shepard, Kenneth L.

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  2. 2
    Data retention in MLC NAND flash memory: Characterization, optimization, and recovery

    Data retention in MLC NAND flash memory: Characterization, optimization, and recovery by Yu Cai, Yixin Luo, Haratsch, Erich F., Ken Mai, Mutlu, Onur

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  3. 3
    Threshold voltage distribution in MLC NAND flash memory: Characterization, analysis, and modeling

    Threshold voltage distribution in MLC NAND flash memory: Characterization, analysis, and modeling by Cai, Yu, Haratsch, Erich F., Mutlu, Onur, Mai, Ken

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  4. 4
    Vulnerabilities in MLC NAND Flash Memory Programming: Experimental Analysis, Exploits, and Mitigation Techniques

    Vulnerabilities in MLC NAND Flash Memory Programming: Experimental Analysis, Exploits, and Mitigation Techniques by Yu Cai, Ghose, Saugata, Yixin Luo, Ken Mai, Mutlu, Onur, Haratsch, Erich F.

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  5. 5
    Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation

    Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation by Yu Cai, Mutlu, Onur, Haratsch, Erich F., Ken Mai

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  6. 6
    A secure camouflaged logic family using post-manufacturing programming with a 3.6GHz adder prototype in 65nm CMOS at 1V nominal VDD

    A secure camouflaged logic family using post-manufacturing programming with a 3.6GHz adder prototype in 65nm CMOS at 1V nominal VDD by Akkaya, Nail Etkin Can, Erbagci, Burak, Ken Mai

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  7. 7
    Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime

    Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime by Yu Cai, Yalcin, G., Mutlu, O., Haratsch, E. F., Cristal, A., Unsal, O. S., Ken Mai

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  8. 8
    Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?

    Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs? by Chung, E S, Milder, P A, Hoe, J C, Mai, Ken

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  9. 9
    Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding

    Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding by Jangwoo Kim, Hardavellas, N., Ken Mai, Falsafi, B., Hoe, J.C.

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  10. 10
    Highly Parallel FPGA Emulation for LDPC Error Floor Characterization in Perpendicular Magnetic Recording Channel

    Highly Parallel FPGA Emulation for LDPC Error Floor Characterization in Perpendicular Magnetic Recording Channel by Yu Cai, Seungjune Jeon, Ken Mai, Kumar, B.V.K.V.

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  11. 11
    MAV-NPU: A 22nm Sparse Neural Network Processor for Real-Time, Resolution-Scalable Vision of Autonomous Micro Aerial Vehicles

    MAV-NPU: A 22nm Sparse Neural Network Processor for Real-Time, Resolution-Scalable Vision of Autonomous Micro Aerial Vehicles by Chen, Siyuan, Mai, Ken

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  12. 12
    Towards Specialized Hardware for Learning-based Visual Odometry on the Edge

    Towards Specialized Hardware for Learning-based Visual Odometry on the Edge by Chen, Siyuan, Mai, Ken

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  13. 13
    Comparison of bi-stable and delay-based Physical Unclonable Functions from measurements in 65nm bulk CMOS

    Comparison of bi-stable and delay-based Physical Unclonable Functions from measurements in 65nm bulk CMOS by Bhargava, M., Cakir, C., Ken Mai

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  14. 14
    6T SRAM and 3T DRAM data retention and remanence characterization in 65nm bulk CMOS

    6T SRAM and 3T DRAM data retention and remanence characterization in 65nm bulk CMOS by Cakir, C., Bhargava, M., Ken Mai

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  15. 15
    Error patterns in MLC NAND flash memory: measurement, characterization, and analysis

    Error patterns in MLC NAND flash memory: measurement, characterization, and analysis by Cai, Yu, Haratsch, Erich F., Mutlu, Onur, Mai, Ken

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  16. 16
    SCAN-PUF: A low overhead Physically Unclonable Function from scan chain power-up states

    SCAN-PUF: A low overhead Physically Unclonable Function from scan chain power-up states by Niewenhuis, Ben, Blanton, R. D., Bhargava, Mudit, Ken Mai

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  17. 17
    In-Situ Observation of Circuit Behavior Using Pump-Probe Laser Voltage Probe Technique

    In-Situ Observation of Circuit Behavior Using Pump-Probe Laser Voltage Probe Technique by King, M. P., Beutler, J., Smith, N., Kohl, I., Meisenheimer, T., Atli, A. O., Mohan, P., Mai, K.

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  18. 18
    Hardware Redaction via Designer-Directed Fine-Grained eFPGA Insertion

    Hardware Redaction via Designer-Directed Fine-Grained eFPGA Insertion by Mohan, Prashanth, Atli, Oguz, Sweeney, Joseph, Kibar, Onur, Pileggi, Larry, Mai, Ken

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  19. 19
    Evaluating the Impact of Repetition, Redundancy, Scrubbing, and Partitioning on 28-nm FPGA Reliability Through Neutron Testing

    Evaluating the Impact of Repetition, Redundancy, Scrubbing, and Partitioning on 28-nm FPGA Reliability Through Neutron Testing by Kibar, Ogun O., Mohan, Prashanth, Rech, Paolo, Mai, Ken

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  20. 20
    Mismatch analysis and statistical design at 65 nm and below

    Mismatch analysis and statistical design at 65 nm and below by Pileggi, L., Keskin, G., Xin Li, Ken Mai, Proesel, J.

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