The critical oxide thickness for Pb-free reflow soldering on Cu substrate by Chung, C. Key, Chen, Y.J., Li, C.C., Kao, C.R.

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Thermal Stress of Surface Oxide Layer on Micro Solder Bumps During Reflow by Key Chung, C., Zhu, Z. X., Kao, C. R.

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Reactions of Sn-4.0Ag-0.5Cu on Cu and Electroless Ni Substrate in Premelting Soldering Process by Chung, C. Key, Chen, Y. J., Yang, T. L., Kao, C. R.

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Roles of phosphorous in Sn4Ag0.5Cu solder reaction with electrolytic Ni–Au by Key Chung, C., Huang, T.C., Shia, R., Yang, T.L., Kao, C.R.

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Direct evidence for a Cu-enriched region at the boundary between Cu6Sn5 and Cu3Sn during Cu/Sn reaction by Chung, C. Key, Duh, Jenq-Gong, Kao, C.R.

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Challenges of large Fan out multi-chip module and fine Cu line space by Lung Huang, Yu, Key Chung, C., Lin, C. F., Hua LU, Guan, Hung Tseng, Ching, Da Chang, Hong, Hsun Hsu, Chih, Xu, Bruce

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Mechanisms and solutions to the brittle solder joint in electroless Ni plating by Wang, Xuan, Chung, C. Key

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3D FO package technology using bridge die for high number of chiplets integration by Zhuang, Jiaming, Li, Shangxuan, Zhang, Xc, Chen, Ivan, Chen, Bruce, Hsieh, Simon, Yang, Bohan, Chung, C. Key, Xia, Xin

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Origin and evolution of voids in electroless Ni during soldering reaction by Chung, C. Key, Chen, Y.J., Chen, W.M., Kao, C.R.

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Generational changes of flip chip interconnection technology by Wen Shan Tsai, Huang, C. Y., Chung, C. Key, Yu, K. H., Lin, C. F.

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The challenge of Fan-out WLP in different process flow by Hsueh, Yu-Ting, Chang, Hong-Da, Tseng, Wallace, Lin, C. F., Key Chung, C.

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Board Level Reliability of Thinner Stacking Chips Package with Through Silicon Via Interposer by Tsai, Wen Shan, Hsu, Bruce, Chang, Fred, Huang, Yun Long, Lin, Joe, Lin, C. F., Key Chung, C.

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Direct evidence for a Cu-enriched region at the boundary between Cu 6Sn 5 and Cu 3Sn during Cu/Sn reaction by Chung, C. Key, Duh, Jenq-Gong, Kao, C.R.

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Scalable Chiplet package using Fan-Out Embedded Bridge by Lin, Joe, Chung, C. Key, Lin, C. F., Liao, Ally, Lu, Ying Ju, Shuang Chen, Jia, Ng, Daniel

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Electrical Performances of Fan-Out Embedded Bridge by You, JinWei, Li, Jay, Ho, David, Li, Jackson, Zhuang, Ming Han, Lai, David, Chung, C. Key, Wang, Yu-Po

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The interactions of lead (Pb) in lead free solder (Sn/Ag/Cu) system by Key Chung, C., Aspandiar, R., Foo Leong, K., Cheng Siew Tay

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Highly Thermal Dissipation for Large HPC Package Using Liquid Metal Materials by Huang, Yu Lung, Chung, C. Key, Lin, C.F., Yu, Kuo Haw, Lin, Rung Jeng, Hong, Wilson

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3D Micro Bump Interface Enabling Top Die Interconnect to True Circuit Through Silicon Via Wafer by Chang, Nistec, Chung, C. Key, Wang, Yu-Po, Lin, C. F., Su, PJ, Shih, Teny, Kao, Nicholas, Hung, Joe

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LTD PKG. (Liquid Thermal Dissipation Package) Technology by Huang, Yu Lung, Chung, C. Key, Lin, C.F., Xu, Bruce, Liao, Yunn Shiuan

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Comparison of 3D Packages with 20 \mu \mathrm bump pitch using reflow soldering and thermal compression bonding by Chan, Mu Hsuan, Chuang, Chris, Huang, Yu Lung, Chen, Wei Jhen, Jiang, Don Son, Huang, C.M., Chung, C. Key

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