Texture Classification Using Dominant Neighborhood Structure by Khellah, Fakhry M.

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A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance by Bowman, K A, Tschanz, J W, Lu, S L, Aseron, P A, Khellah, M M, Raychowdhury, A, Geuskens, B M, Tokunaga, C, Wilkerson, C B, Karnik, T, De, V K

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Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating by Minki Cho, Kim, Stephen T., Tokunaga, Carlos, Augustine, Charles, Kulkarni, Jaydeep P., Ravichandran, Krishnan, Tschanz, James W., Khellah, Muhammad M., De, Vivek

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2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology by Somasekhar, D., Yibin Ye, Aseron, P., Shih-Lien Lu, Khellah, M.M., Howard, J., Ruhl, G., Karnik, T., Borkar, S., De, V.K., Keshavarzi, A.

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Accurate Estimation of SRAM Dynamic Stability by Khalil, D.E., Khellah, M., Nam-Sung Kim, Ismail, Y., Karnik, T., De, V.K.

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All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control by Bowman, K. A., Tokunaga, C., Tschanz, J. W., Raychowdhury, A., Khellah, M. M., Geuskens, B. M., Lu, Shih-Lien L., Aseron, P. A., Karnik, T., De, V. K.

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A 0.45-1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS by Jain, Rinkle, Geuskens, Bibiche M., Kim, Stephen T., Khellah, Muhammad M., Kulkarni, Jaydeep, Tschanz, James W., De, Vivek

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Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator by Kim, Stephen T., Yi-Chun Shih, Mazumdar, Kaushik, Jain, Rinkle, Ryan, Joseph F., Tokunaga, Carlos, Augustine, Charles, Kulkarni, Jaydeep P., Ravichandran, Krishnan, Tschanz, James W., Khellah, Muhammad M., De, Vivek

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Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays by Raychowdhury, Arijit, Geuskens, Bibiche M, Bowman, Keith A, Tschanz, James W, Lu, Shih-Lien L, Karnik, Tanay, Khellah, Muhammad M, De, Vivek K

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Serial-Link Bus: A Low-Power On-Chip Bus Architecture by Ghoneima, M., Ismail, Y., Khellah, M.M., Tschanz, J., De, V.

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Introduction to the January Special Issue on the 2017 IEEE International Solid-State Circuits Conference by Bowman, Keith A., Khellah, Muhammad M., Kono, Takashi, Shor, Joseph, Mak, Pui-In

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Formal derivation of optimal active shielding for low-power on-chip buses by Ghoneima, M., Ismail, Y.I., Khellah, M.M., Tschanz, J.W., De, V.

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Process, Temperature, and Supply-Noise Tolerant 45 ~nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits by Khellah, M., Nam Sung Kim, Yibin Ye, Somasekhar, D., Karnik, T., Borkar, N., Pandya, G., Hamzaoglu, F., Coan, T., Yih Wang, Zhang, K., Webb, C., De, V.

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SSMCB: Low-Power Variation-Tolerant Source-Synchronous Multicycle Bus by Ghoneima, M., Ismail, Y., Khellah, M., De, V.

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An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and } Optimization by Meinerzhagen, Pascal A., Tokunaga, Carlos, Malavasi, Andres, Vaidya, Vaibhav, Mendon, Ashwin, Mathaikutty, D., Kulkarni, Jaydeep, Augustine, Charles, Cho, Minki, Kim, Stephen T., Matthew, George E., Jain, Rinkle, Ryan, Joseph, Peng, Chung-Ching, Paul, Somnath, Vangal, Sriram, Perez Esparza, Brando, Cuellar, L., Woodman, M., Iyer, Bala, Maiyuran, Subramaniam, Chinya, G., Zou, Xiang, Liao, Yuyun, Ravichandran, Krishnan, Wang, H., Khellah, Muhammad M., Tschanz, James W., De, Vivek

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Characterization of Inverse Temperature Dependence in logic circuits by Cho, M., Khellah, M., Chae, K., Ahmed, K., Tschanz, J., Mukhopadhyay, S.

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Variations-Aware Low-Power Design and Block Clustering With Voltage Scaling by Azizi, N., Khellah, M.M., De, V.K., Najm, F.N.

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PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction by Raychowdhury, A., Geuskens, B., Kulkarni, J., Tschanz, J., Bowman, K., Karnik, T., Shih-Lien Lu, De, V., Khellah, M.M.

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Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS by Meinerzhagen, Pascal A., Kundu, Sandip, Malavasi, Andres, Nguyen, Trang, Khellah, Muhammad M., Tschanz, James W., De, Vivek

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Trading Off Cache Capacity for Low-Voltage Operation by Wilkerson, C., Hongliang Gao, Alameldeen, A.R., Chishti, Z., Khellah, M., Shih-Lien Lu

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