Search Results - Kim, Kwi-Dong

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  1. 1
    A Dual-Channel Pipelined ADC With Sub-ADC Based on Flash-SAR Architecture

    A Dual-Channel Pipelined ADC With Sub-ADC Based on Flash-SAR Architecture by Jeon, Young-Deuk, Nam, Jae-Won, Kim, Kwi-Dong, Roh, Tae Moon, Kwon, Jong-Kee

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  2. 2
    A Low‐Spur CMOS PLL Using Differential Compensation Scheme

    A Low‐Spur CMOS PLL Using Differential Compensation Scheme by Yun, Seok‐Ju, Kim, Kwi‐Dong, Kwon, Jong‐Kee

    Published in ETRI journal
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  3. 3
    A Wide-Tuning Dual-Band Transformer-Based Complementary VCO

    A Wide-Tuning Dual-Band Transformer-Based Complementary VCO by YUN, Seok-Ju, HUI DONG LEE, KIM, Kwi-Dong, LEE, Sang-Gug, KWON, Jong-Kee

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  4. 4
    A 10-bit 400-MS/s 160-mW 0.13-μm CMOS dual-channel pipeline ADC without channel mismatch calibration

    A 10-bit 400-MS/s 160-mW 0.13-μm CMOS dual-channel pipeline ADC without channel mismatch calibration by LEE, Seung-Chul, KIM, Kwi-Dong, KWON, Jong-Kee, KIM, Jongdae, LEE, Seung-Hoon

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  5. 5
    A Low-Spur CMOS PLL Using Differential Compensation Scheme

    A Low-Spur CMOS PLL Using Differential Compensation Scheme by Yun, Seok-Ju, Kim, Kwi-Dong, Kwon, Jong-Kee

    Published in ETRI journal
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  6. 6
    A 10-bit 400-MS/s 160-mW 0.13-/spl mu/m CMOS dual-channel pipeline ADC without channel mismatch calibration

    A 10-bit 400-MS/s 160-mW 0.13-/spl mu/m CMOS dual-channel pipeline ADC without channel mismatch calibration by Lee, Seung-Chul, Kim, Kwi-Dong, Kwon, Jong-Kee, Kim, Jongdae, Lee, Seung-Hoon

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  7. 7
    Fabrication of Ferroelectric Gate Memory Device Using BLT/HfO 2 /Si Gate Structure

    Fabrication of Ferroelectric Gate Memory Device Using BLT/HfO 2 /Si Gate Structure by Yoon, Sung-Min, You, In-Kyu, Lee, Nam-Yeal, Kim, Kwi-Dong, Cho, Seong-Mok, Ryu, Sang-Ouk, Shin, Woong-Chul, Choi, Kyu-Jung, Yu, Byoung-Gon

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  8. 8
    Etching Mechanism of Ferroelectric Film Etched by Helicon Plasma Method

    Etching Mechanism of Ferroelectric Film Etched by Helicon Plasma Method by You, In-Kyu, Yoon, Sung-Min, Cho, Seong Mok, Kim, Kwi Dong, Ryu, Sang-Ouk, Lee, Nam Yeal, Yu, Byoung-Gon, Koo, Jin Gun, Kim, Jong Dae

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  9. 9
    MATERIAL DESIGN SCHEMES FOR SINGLE-TRANSISTOR-TYPE FERROELECTRIC MEMORY CELLS USING Pt/(Bi,La)4Ti3O12/ONO/Si STRUCTURES

    MATERIAL DESIGN SCHEMES FOR SINGLE-TRANSISTOR-TYPE FERROELECTRIC MEMORY CELLS USING Pt/(Bi,La)4Ti3O12/ONO/Si STRUCTURES by N-Y, Lee, S-M, Yoon, I-K, You, S-O, Ryu, S-M, Cho, W-C, Shin, K-J, Choi

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  10. 10
    Analysis of the electrical characteristics of novel ESD protection device with high holding voltage under various temperatures

    Analysis of the electrical characteristics of novel ESD protection device with high holding voltage under various temperatures by Jong-Il Won, Hyun-Duck Lee, Kang-Yoon Lee, Kwi-Dong Kim, Yong-Seo Koo

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  11. 11
    The design of DC-DC converter with DT-CMOS for portable terminal

    The design of DC-DC converter with DT-CMOS for portable terminal by Ka-San Ha, Jae-Hwan Ha, Kang-Yoon Lee, Kwi-Dong Kim, Yong-Seo Koo

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  12. 12
    Design of Gate-Ground-NMOS-Based ESD Protection Circuits with Low Trigger Voltage, Low Leakage Current, and Fast Turn-On

    Design of Gate-Ground-NMOS-Based ESD Protection Circuits with Low Trigger Voltage, Low Leakage Current, and Fast Turn-On by Koo, Yong-Seo, Kim, Kwang-Soo, Park, Shi-Hong, Kim, Kwi-Dong, Kwon, Jong-Kee

    Published in ETRI journal
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  13. 13
    A 105.5 dB, 0.49 mm2 Audio ΣΔ modulator using chopper stabilization and fully randomized DWA

    A 105.5 dB, 0.49 mm2 Audio ΣΔ modulator using chopper stabilization and fully randomized DWA by Yi-Gyeong Kim, Min-Hyung Cho, Kwi-Dong Kim, Jong-Kee Kwon, Jongdae Kim

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  14. 14
    A 9.15mW 0.22mm2 10b 204MS/s pipelined SAR ADC in 65nm CMOS

    A 9.15mW 0.22mm2 10b 204MS/s pipelined SAR ADC in 65nm CMOS by Young-Deuk Jeon, Young-Kyun Cho, Jae-Won Nam, Kwi-Dong Kim, Woo-Yol Lee, Kuk-Tae Hong, Jong-Kee Kwon

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  15. 15
    A 4.7mW 0.32mm2 10b 30MS/s Pipelined ADC Without a Front-End S/H in 90nm CMOS

    A 4.7mW 0.32mm2 10b 30MS/s Pipelined ADC Without a Front-End S/H in 90nm CMOS by Jeon, Young-Deuk, Lee, Seung-Chul, Kim, Kwi-Dong, Kwon, Jong-Kee, Kim, Jongdae

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  16. 16
    A 5-mW 0.26-mm2 10-bit 20-MS/s Pipelined CMOS ADC with Multi-Stage Amplifier Sharing Technique

    A 5-mW 0.26-mm2 10-bit 20-MS/s Pipelined CMOS ADC with Multi-Stage Amplifier Sharing Technique by Young-Deuk Jeon, Seung-Chul Lee, Kwi-Dong Kim, Jong-Kee Kwon, Jongdae Kim, Dongsoo Park

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  17. 17
    A 10b 205MS/s 1mm2 90nm CMOS Pipeline ADC for Flat-Panel Display Applications

    A 10b 205MS/s 1mm2 90nm CMOS Pipeline ADC for Flat-Panel Display Applications by Lee, Seung-Chul, Jeon, Young-Deuk, Kim, Kwi-Dong, Kwon, Jong-Kee, Kim, Jongdae, Moon, Jeong-Woong, Lee, Wooyol

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  18. 18
    Material Design Schemes for Single-Transistor-Type Ferroelectric Memory Cells Using Pt/(Bi,La) 4 Ti 3 O 12 /ONO/Si Structures

    Material Design Schemes for Single-Transistor-Type Ferroelectric Memory Cells Using Pt/(Bi,La) 4 Ti 3 O 12 /ONO/Si Structures by Lee, Nam-Yeal, Yoon, Sung-Min, You, In-Kyu, Ryu, Sang-Ouk, Cho, Seong-Mok, Shin, Woong-Chul, Choi, Kyu-Jung, Kim, Kwi-Dong, Yu, Byoung-Gon

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  19. 19
    Device characterization and Fabrication Issues for Ferroelectric Gate Field Effect Transistor Device

    Device characterization and Fabrication Issues for Ferroelectric Gate Field Effect Transistor Device by Yu, Byoung-Gon, You, In-Kyu, Lee, Won-Jae, Ryu, Sang-Ouk, Kim, Kwi-Dong, Yoon, Sung-Min, Cho, Seong-Mok, Lee, Nam-Yeal, Shin, Woong-Chul

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  20. 20
    Fabrication of Ferroelectric Gate Memory Device Using BLT/HfO2/Si Gate Structure

    Fabrication of Ferroelectric Gate Memory Device Using BLT/HfO2/Si Gate Structure by Yoon, Sung-Min, You, In-Kyu, Lee, Nam-Yeal, Kim, Kwi-Dong, Cho, Seong-Mok, Ryu, Sang-Ouk, Shin, Woong-Chul, Choi, Kyu-Jung, Yu, Byoung-Gon

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