2097 Impact of mechanism underlying increased serum iron levels during FOLFOX/FOLFIRI therapy by Ochiai, T, Nishimura, K, Watanabe, T, Kitajima, M, Nakatani, A, Nagayasu, K, Naito, S, Takeda, M, Abe, Y, Hara, C, Sato, T, Kishine, K, Nagaoka, I

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A Burst-Mode 3R Receiver for 10-Gbit/s PON Systems With High Sensitivity, Wide Dynamic Range, and Fast Response by Nishihara, S., Kimura, S., Yoshida, T., Nakamura, M., Terada, J., Nishimura, K., Kishine, K., Kato, K., Ohtomo, Y., Yoshimoto, N., Imai, T., Tsubokawa, M.

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Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/s one-chip optical receiver IC with 1: 8 DEMUX by Kishine, K., Ishii, K., Ichino, H.

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PLL design technique by a loop-trajectory analysis taking decision-circuit phase margin into account for over-10-Gb/s clock and data recovery circuits by Kishine, K., Fujimoto, K., Kusanagi, S., Ichino, H.

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A jitter suppression technique for a 2.48832-Gb/s clock and data recovery circuit by Ishii, K., Kishine, K., Ichino, H.

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A 2.5-Gb/s clock and data recovery IC with tunable jitter characteristics for use in LANs and WANs by Kishine, K., Ishihara, N., Takiguchi, K., Ichino, H.

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A high-speed, low-power bipolar digital circuit for Gb/s LSI's: current mirror control logic by Kishine, K., Kobayashi, Y., Ichino, H.

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Mechanism underlying the transient increase of serum iron during FOLFOX/FOLFIRI therapy by OCHIAI, TAKUMI, NISHIMURA, KAZUHIKO, WATANABE, TOMOO, KITAJIMA, MASAYUKI, NAKATANI, AKINORI, SATO, TSUYOSHI, KISHINE, KENJI, FUTAGAWA, SHUNJI, MASHIKO, SATOMI, NAGAOKA, ISAO

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Design method for an over-IO-Gb/s CMOS CML buffer circuit for delay control by Kishine, K., Inaba, H., Ohtomo, Y., Nakamura, M.

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Reliability of molecular weight determination methods for oligomers investigated using certified polystyrene reference materials by Saito, Takeshi, Lusenkova, Marina A., Matsuyama, Shigetomo, Shimada, Kayori, Itakura, Masanao, Kishine, Kana, Sato, Keisuke, Kinugasa, Shinichi

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A 16Gbps laser-diode driver with interwoven peaking inductors in 0.18-µm CMOS by Kuboki, T, Ohtomo, Y, Tsuchiya, A, Kishine, K, Onodera, H

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Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/s one-chip optical receiver IC with 1: 8 DEMU by Kishine, K, Ishii, K, Ichino, H

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An electric power conversion system composed of two parallel-connected converters providing different output currents by Inaba, H., Kishine, K., Igura, Y.

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A 25-Gb/s LD driver with area-effective inductor in a 0.18-µm CMOS by Kuboki, T., Ohtomo, Y., Tsuchiya, A., Kishine, K., Onodera, H.

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A 16Gb/s area-efficient LD driver with interwoven inductor in a 0.18µm CMOS by Kuboki, T., Ohtomo, Y., Tsuchiya, A., Kishine, K., Onodera, H.

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A 10.3Gbps translmpedance amplifier with mutually coupled inductors in 0.18-μm CMOS by Miyawaki, S., Nakamura, M., Tsuchiya, A., Kishine, K., Onodera, H.

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Bandwidth enhancement for high speed amplifier utilizing mutually coupled on-chip inductors by Tsuchiya, A., Kuboki, T., Ohtomo, Y., Kishine, K., Miyawaki, S., Nakamura, M., Onodera, H.

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Contribution of inner shell electrons to position-dependent stopping powers of a crystal surface by Narumi, Kazumasa, Fujii, Yoshikazu, Kishine, Keiji, Kurakake, Hiroshi, Kimura, Kenji, Mannami, Michi-hiko

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A 10G Burst-Mode PIN-TIA Module with 10-nsec Response for PON Systems by Nakamura, M., Nishihara, S., Nishimura, K., Kishine, K., Kimura, S., Yoshida, T., Ohtomo, Y., Yoshimoto, N., Kato, K.

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A fast-response and high-sensitivity PIN-TIA module with wide dynamic range for 10 G burst-mode transmissions by Nishihara, S, Nakamura, M, Nishimura, K, Kishine, K, Kimura, S, Kato, K

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