Search Results - Kishore, K Lal

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  1. 1
    3.6 mw low power wireless RF receiver front end using creative current recycle technique

    3.6 mw low power wireless RF receiver front end using creative current recycle technique by Damodara Venkata Appala Naidu, T., Madhavi, B. K., Lal Kishore, K.

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  2. 2
    Design and performance analysis of digitally controlled multi-mode multi-band power amplifier for Sub-6 GHz applications

    Design and performance analysis of digitally controlled multi-mode multi-band power amplifier for Sub-6 GHz applications by Racha, Ganesh, Kishore, K Lal, Kamatham, Yedukondalu, Perumalla, Srinivasa Rao

    Published in e-Prime
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  3. 3
    FPGA Implementation of 5G NR Primary and Secondary Synchronization

    FPGA Implementation of 5G NR Primary and Secondary Synchronization by Ramesh Kumar, Aytha, Lal Kishore, K.

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  4. 4
    Trends in VLSI Technology - Rural Applications Perspective

    Trends in VLSI Technology - Rural Applications Perspective by Kishore, K Lal

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  5. 5
    Power Analysis and Optimization Techniques of an 8-bit FIR Filter from RTL through GDSII

    Power Analysis and Optimization Techniques of an 8-bit FIR Filter from RTL through GDSII by Kumar, C Ashok, Madhavi, B K, Kishore, K Lal

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  6. 6
    Enhanced Clock Gating Technique for Power Optimization in SRAM and Sequential Circuit

    Enhanced Clock Gating Technique for Power Optimization in SRAM and Sequential Circuit by Ashok Kumar, Cheeli, Madhavi, B.K., Kishore, K. Lal

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  7. 7
    Implementation of 5G NR Primary and Secondary Synchronization

    Implementation of 5G NR Primary and Secondary Synchronization by Kumar, Aytha Ramesh, Kishore, K Lal, Fatima, Amreen

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  8. 8
    Low Leakage CNTFET SRAM Cells

    Low Leakage CNTFET SRAM Cells by Somineni, Rajendra Prasad, Madhavi, B.K., Kishore, K. Lal

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  9. 9
    Design of a 32nm 7T SRAM Cell based on CNTFET for low power operation

    Design of a 32nm 7T SRAM Cell based on CNTFET for low power operation by Prasad, S. Rajendra, Madhavi, B. K., Kishore, K. Lal

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  10. 10
    Dimensional Dependence of Voltage Coefficient of Resistance (αv) for PMNPT Based Varistors

    Dimensional Dependence of Voltage Coefficient of Resistance (αv) for PMNPT Based Varistors by Narasimham, K. V. N. S. V. P. L., Kishore, K. Lal

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  11. 11
    Super Resolution Reconstruction in Mixed Noise Environment

    Super Resolution Reconstruction in Mixed Noise Environment by Devi, A Geetha, Madhu, T, Kishore, K Lal

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  12. 12
    A 80Ms/sec 10bit PIPELINED ADC Using 1.5Bit Stages And Built-in Digital Error Correction Logic

    A 80Ms/sec 10bit PIPELINED ADC Using 1.5Bit Stages And Built-in Digital Error Correction Logic by Rao, P Prasad, Kishore, K Lal

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  13. 13
    Dynamic spectrum management scheme in a smart software radio

    Dynamic spectrum management scheme in a smart software radio by Rallapalli, H., Lal Kishore, K.

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  14. 14
    A Technique to Reduce Glitch Power during Physical Design Stage for Low Power and Less IR Drop

    A Technique to Reduce Glitch Power during Physical Design Stage for Low Power and Less IR Drop by KumarB.V.P, Vasantha, S. Murthy Sharma, N., Lal Kishore, K.

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  15. 15
    Power optimized programmable embedded controller

    Power optimized programmable embedded controller by Kamaraju, M, K Lal Kishore, Tilak, A V N

    Published in arXiv.org
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  16. 16
    Efficient Crosstalk Reduction Technique for Data Bus

    Efficient Crosstalk Reduction Technique for Data Bus by Sathish, A, Latha, M Madhavi, Kishore, K Lal

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  17. 17
    A Novel Approach to Reduce Leakage Power in GALS System architectures

    A Novel Approach to Reduce Leakage Power in GALS System architectures by Rajakumari, A, Murthy Sharma, N S, Kishore, K Lal

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  18. 18
    Efficient Switching Activity Reduction Technique for Fault Tolerant Data Bus

    Efficient Switching Activity Reduction Technique for Fault Tolerant Data Bus by Sathish, A, Latha, M Madhavi, Kishore, K Lal

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  19. 19
    A technique to eliminate glitch power consumption at physical design stage in CMOS circuits

    A technique to eliminate glitch power consumption at physical design stage in CMOS circuits by Kumar, Vasantha B. V. P., Sharma, N. S. Murthy, Kishore, K. Lal, Vivekanand, M., Raju, K. Murthy, Swetha, S. Divya

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  20. 20
    Design of Low Write-Power Consumption SRAM Cell Based on CNTFET at 32nm Technology

    Design of Low Write-Power Consumption SRAM Cell Based on CNTFET at 32nm Technology by Rajendra Prasad, S

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