Search Results - Kittl, Jorge E

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  1. 1
    AgZn system β - β' order-disorder phase transition

    AgZn system β - β' order-disorder phase transition by Arias, Delia, Kittl, Jorge E

    Published in Scripta metallurgica
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  2. 2
    AgZn system β′ → ζ0 and β → ζ0 phase transformation

    AgZn system β′ → ζ0 and β → ζ0 phase transformation by Arias, Delia, Kittl, Jorge E.

    Published in Metallography
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  3. 3
    Manufacturable Processes for < 32-nm-node CMOS Enhancement by Synchronous Optimization of Strain-Engineered Channel and External Parasitic Resistances

    Manufacturable Processes for < 32-nm-node CMOS Enhancement by Synchronous Optimization of Strain-Engineered Channel and External Parasitic Resistances by NOORI, Atif M, BALSEANU, Mihaela, LAUWERS, Anne, LEE, Wen-Chin, JIANXIN LEI, MANDREKAR, Tushar, SCHREUTELKAMP, Robert, SHAH, Kavita, THOMPSON, Scott E, VERHEYEN, Peter, WANG, Ching-Ya, XIA, Li-Qun, BOELEN, Pieter, ARGHAVANI, Reza, COCKBUM, Andrew, DEMUYNCK, Steven, FELCH, Susan, GANDIKOTA, Srinivas, JERRY GELATOS, A, KHANDELWAL, Amit, KITTL, Jorge A

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  4. 4
    Ni fully GermanoSilicide for gate electrode application in pMOSFETs with HfSiON gate dielectrics

    Ni fully GermanoSilicide for gate electrode application in pMOSFETs with HfSiON gate dielectrics by Hong Yu Yu, Singanamalla, R., Simoen, E., Xiaoping Shi, Lauwers, A., Kittl, J.A., Van Elshocht, S., Kristin De Meyer, Absil, P., Jurczak, M., Biesemans, S.

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  5. 5
    Manufacturable Processes for \leq 32-nm-node CMOS Enhancement by Synchronous Optimization of Strain-Engineered Channel and External Parasitic Resistances

    Manufacturable Processes for \leq 32-nm-node CMOS Enhancement by Synchronous Optimization of Strain-Engineered Channel and External Parasitic Resistances by Noori, A.M., Balseanu, M., Boelen, P., Cockburn, A., Demuynck, S., Felch, S., Gandikota, S., Gelatos, A.J., Khandelwal, A., Kittl, J.A., Lauwers, A., Wen-Chin Lee, Jianxin Lei, Mandrekar, T., Schreutelkamp, R., Shah, K., Thompson, S.E., Verheyen, P., Ching-Ya Wang, Li-Qun Xia, Arghavani, R.

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  6. 6
    A novel tensile Si (n) and compressive SiGe (p) dual-channel CMOS FinFET co-integration scheme for 5nm logic applications and beyond

    A novel tensile Si (n) and compressive SiGe (p) dual-channel CMOS FinFET co-integration scheme for 5nm logic applications and beyond by Bae, Dong-il, Bae, Geumjong, Bhuwalka, Krishna K, Lee, Seung-Hun, Song, Myung-Geun, Jeon, Taek-soo, Kim, Cheol, Kim, Wookje, Park, Jaeyoung, Kim, Sunjung, Kwon, Uihui, Jeon, Jongwook, Nam, Kab-Jin, Lee, Sangwoo, Lian, Sean, Seo, Kang-ill, Lee, Sun-Ghil, Jae Hoo Park, Heo, Yeon-Cheol, Rodder, Mark S., Kittl, Jorge A., Kim, Yihwan, Hwang, Kihyun, Kim, Dong-Won, Liang, Mong-song, Jung, E.S.

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  7. 7
    Ni-based silicides: Material issues for advanced CMOS applications

    Ni-based silicides: Material issues for advanced CMOS applications by KITTL, Jorge A, LAUWERS, Anne, CHAMIRIAN, Oxana, VAN DAL, Mark, AKHEYAR, Amal, RICHARD, Olivier, LISONI, Judit G, DE POTTER, Muriel, LINDSAY, Richard, MAEX, Karen

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  8. 8
    Salicides and alternative technologies for future ICs

    Salicides and alternative technologies for future ICs by Kittl, Jorge A, Shiau, Wei-Tsun, Miles, Donald, Violette, Katherine E, Hu, Jerry C, Hong, Qi-Zhong

    Published in Solid state technology
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  9. 9
    Salicides and alternative technologies for future ICs: part I

    Salicides and alternative technologies for future ICs: part I by Kittl, Jorge A, Shiau, Wei-Tsun, Miles, Donald, Violette, Katherine E, Hu, Jerry C, Hong, Qi-Zhong

    Published in Solid state technology
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