SmartReflex Power and Performance Management Technologies for 90 nm, 65 nm, and 45 nm Mobile Application Processors by Gammie, Gordon, Wang, Alice, Mair, Hugh, Lagerquist, Rolf, Chau, Minh, Royannez, Philippe, Gururajarao, Sumanth, Ko, Uming

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Enabling simultaneously bi-directional TSV signaling for energy and area efficient 3D-ICs by Sunghyun Park, Wang, Alice, Uming Ko, Li-Shiuan Peh, Chandrakasan, Anantha P.

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A 28nm 0.6V low-power DSP for mobile applications by Gammie, G, Ickes, N, Sinangil, M E, Rithe, R, Gu, J, Wang, A, Mair, H, Datla, S, Bing Rong, Honnavara-Prasad, S, Lam Ho, Baldwin, G, Buss, D, Chandrakasan, A P, Uming Ko

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High-performance energy-efficient D-flip-flop circuits by Uming Ko, Balsara, P.T.

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23.3 A highly integrated smartphone SoC featuring a 2.5GHz octa-core CPU with advanced high-performance and low-power techniques by Mair, Hugh, Gammie, Gordon, Wang, Alice, Gururajarao, Sumanth, Lin, Ichiro, HsinChen Chen, Wuan Kuo, Rajagopalan, Anand, Wei-Zheng Ge, Lagerquist, Rolf, Rahman, Syed, Chung, C. J., Wang, Simon, Lee-Kee Wong, Yi-Chang Zhuang, Li, Kent, Jidong Wang, Minh Chau, Yijing Liu, Dia, Daniel, Peng, Mark, Uming Ko

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90nm low leakage SoC design techniques for wireless applications by Royannez, P., Mair, H., Dahan, F., Wagner, M., Streeter, M., Bouetel, L., Blasquez, J., Clasen, H., Semino, G., Dong, J., Scott, D., Pitts, B., Raibaut, C., Uming Ko

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Introduction to the Special Issue on the 2012 IEEE International Solid-State Circuits Conference by Ortmanns, Maurits, Fischer, Timothy, Ko, Uming, Dehaene, Wim, Takai, Yasuhiro

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Low-power design techniques for high-performance CMOS adders by Uming Ko, Balsara, T., Wai Lee

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A 28 nm 0.6 V Low Power DSP for Mobile Applications by Ickes, N., Gammie, G., Sinangil, M. E., Rithe, R., Gu, J., Wang, A., Mair, H., Datla, S. R., Rong, B., Honnavara-Prasad, S., Ho, L., Baldwin, G., Buss, D., Chandrakasan, A. P., Ko, U.

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Session 2 overview: Technologies for health / technology directions by Ko, Uming, Colinet, Eric

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A 45nm 3.5G Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques by Gammie, Gordon, Wang, Alice, Chau, Minh, Gururajarao, Sumanth, Pitts, Robert, Jumel, Fabien, Engel, Stacey, Royannez, Philippe, Lagerquist, Rolf, Mair, Hugh, Vaccani, Jeff, Baldwin, Greg, Heragu, Keerthi, Mandal, Rituparna, Clinton, Michael, Arden, Don, Ko, Uming

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Entering the hot zone - can you handle the heat and be cool? by Nadamudi, D., Clancy, M., Yang, A., DeLa Cruz, J.A., Chandra, R., Santhanam, S., Burke, S., Uming Ko

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EP3: Empowering the killer SoC applications of 2020 by Borkar, Shekhar, Ko, Uming, Keshavarzi, Ali, Cantatore, Eugenio

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2014 ISSC Demonstration Session Summary: 14/12 Mix of Industry/Academia Papers Offers Something for Everyone [Conference Reports] by Ko, Uming

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A design platform for 90-nm leakage reduction techniques by Royannez, Philippe, Mair, Hugh, Dahan, Franck, Wagner, Mike, Streeter, Mark, Bouetel, Laurent, Blasquez, Joel, Clasen, H., Semino, G., Dong, Julie, Scott, D., Pitts, B., Raibaut, Claudine, Ko, Uming

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3.4 A 10nm FinFET 2.8GHz tri-gear deca-core CPU complex with optimized power-delivery network for mobile SoC performance by Mair, Hugh, Lin, Gordon, Thippana, Achuta, Li, Kent, Rahman, Manzur, Kuo, Wuan, Yen, David, Zhuang, Yi-Chang, Fu, Ue, Wang, Hung-Wei, Peng, Mark, Wang, Ericbill, Wu, Cheng-Yuh, Dosluoglu, Taner, Gelman, Anatoly, Dia, Daniel, Gurumurthy, Girishankar, Hsieh, Tony, Lin, W.X., Tzeng, Ray, Wu, Jengding, Wang, C.H., Wang, Alice, Ko, Uming, Kao, Ping, Tsai, Yuwen, Gururajarao, Sumanth, Lagerquist, Rolf, Son, Jin, Gammie, Gordon

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Short-circuit power driven gate sizing technique for reducing power dissipation by Uming Ko, Balsara, P.T.

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4.3 A 20nm 2.5GHz ultra-low-power tri-cluster CPU subsystem with adaptive power allocation for optimal mobile SoC performance by Mair, Hugh T., Gammie, Gordon, Wang, Alice, Lagerquist, Rolf, Chung, C. J., Gururajarao, Sumanth, Kao, Ping, Rajagopalan, Anand, Saha, Anirban, Jain, Amit, Wang, Ericbill, Ouyang, Shichin, Huajun Wen, Thippana, Achuta, HsinChen Chen, Rahman, Syed, Chau, Minh, Varma, Anshul, Flachs, Brian, Peng, Mark, Tsai, Alfred, Lin, Vincent, Ue Fu, Wuan Kuo, Lee-Kee Yong, Clavin Peng, Leo Shieh, Jengding Wu, Uming Ko

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Solutions for logic and processor core design at the 45nm technology node & and below by Royannez, P., Mair, H., Clinton, M., Uming Ko

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Empowering the Killer SoC Applications of 2020 [Conference Reports] by Ko, Uming, Olstein, Katherine

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