Search Results - Kolar, Pramod

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  1. 1
    Process Technology Variation

    Process Technology Variation by Kuhn, K. J., Giles, M. D., Becher, D., Kolar, P., Kornfeld, A., Kotlyar, R., Ma, S. T., Maheshwari, A., Mudanai, S.

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  2. 2
    A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management

    A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management by Yih Wang, Bhattacharya, U., Hamzaoglu, F., Kolar, P., Yong-Gee Ng, Liqiong Wei, Ying Zhang, Zhang, K., Bohr, M.

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  3. 3
    Sub-550mV SRAM Design in 22nm FinFET Low Power (22FFL) Technology with Self-Induced Collapse Write Assist

    Sub-550mV SRAM Design in 22nm FinFET Low Power (22FFL) Technology with Self-Induced Collapse Write Assist by Kim, Daeyeon, Wiedemer, Jami, Kolar, Pramod, Shrivastava, Ayush, Shah, Jinal, Nalam, Satyanand, Baek, Gwanghyeon, Wang, Xiaofei, Guo, Zheng, Karl, Eric

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  4. 4
    A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation

    A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation by Kolar, P, Karl, E, Bhattacharya, U, Hamzaoglu, F, Nho, H, Yong-Gee Ng, Yih Wang, Zhang, K

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  5. 5
    A 1.1 GHz 12 μA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications

    A 1.1 GHz 12 μA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications by YIH WANG, HONG JO AHN, LIN, Jie-Feng, NG, Yong-Gee, POST, Ian, LIQIONG WEI, YING ZHANG, ZHANG, Kevin, BOHR, Mark, BHATTACHARYA, Uddalak, ZHANPING CHEN, COAN, Tom, HAMZAOGLU, Fatih, HAFEZ, Walid M, JAN, Chia-Hong, KOLAR, Pramod, KULKARNI, Sarvesh H

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  6. 6
    A methodology for yield-specific leakage estimation in memory

    A methodology for yield-specific leakage estimation in memory by Chatterjee, Subho, Kolar, Pramod, Wei Jian Chan, Ko, Jae Y., Pandya, Gunjan H.

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  7. 7
    Process Technology Variation : CHARACTERIZATION OF NANO CMOS VARIABIALITY BY SIMULATION AND MEASUREMENTS

    Process Technology Variation : CHARACTERIZATION OF NANO CMOS VARIABIALITY BY SIMULATION AND MEASUREMENTS by KUHN, Kelin J, GILES, Martin D, BECHER, David, KOLAR, Pramod, KORNFELD, Avner, KOTLYAR, Roza, MA, Sean T, MAHESHWARI, Atul, MUDANAI, Sivakumar

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  8. 8
    Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design

    Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design by Hamzaoglu, Fatih, Yih Wang, Kolar, Pramod, Liqiong Wei, Yong-Gee Ng, Bhattacharya, Uddalak, Zhang, Kevin

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  9. 9
    WinDConv: A Fused Datapath CNN Accelerator for Power-Efficient Edge Devices

    WinDConv: A Fused Datapath CNN Accelerator for Power-Efficient Edge Devices by Mahale, Gopinath, Udupa, Pramod, Chandrasekharan, Kiran Kolar, Lee, Sehwan

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  10. 10
    IKW: Inter-Kernel Weights for Power Efficient Edge Computing

    IKW: Inter-Kernel Weights for Power Efficient Edge Computing by Udupa, Pramod, Mahale, Gopinath, Chandrasekharan, Kiran Kolar, Lee, Sehwan

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  11. 11
    Accelerating Depthwise Convolution and Pooling Operations on z-First Storage CNN Architectures

    Accelerating Depthwise Convolution and Pooling Operations on z-First Storage CNN Architectures by Udupa, Pramod, Mahale, Gopinath, Chandrasekharan, Kiran Kolar, Lee, Sehwan

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