Search Results - Kosonocky, S.V.

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  1. 1
    A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs

    A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs by Suhwan Kim, Kosonocky, S.V., Knebel, D.R., Stawiasz, K., Papaefthymiou, M.C.

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  2. 2
    Reducing Ground-Bounce Noise and Stabilizing the Data-Retention Voltage of Power-Gating Structures

    Reducing Ground-Bounce Noise and Stabilizing the Data-Retention Voltage of Power-Gating Structures by Suhwan Kim, Chang Jun Choi, Deog-Kyoon Jeong, Kosonocky, S.V., Sung Bae Park

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  3. 3
    Introduction to the Special Issue on the 2006 Symposium on VLSI Circuits

    Introduction to the Special Issue on the 2006 Symposium on VLSI Circuits by Kosonocky, S.V., Yano, Kazuo

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  4. 4
    Understanding and minimizing ground bounce during mode transition of power gating structures

    Understanding and minimizing ground bounce during mode transition of power gating structures by Kim, S., Kosonocky, S.V., Knebel, D.R.

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  5. 5
    Optimal supply and threshold scaling for subthreshold CMOS circuits

    Optimal supply and threshold scaling for subthreshold CMOS circuits by Wang, A., Chandrakasan, A.P., Kosonocky, S.V.

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  6. 6
    Low power integrated scan-retention mechanism

    Low power integrated scan-retention mechanism by Zyuban, V., Kosonocky, S.V.

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  7. 7
    Minimizing inductive noise in system-on-a-chip with multiple power gating structures

    Minimizing inductive noise in system-on-a-chip with multiple power gating structures by Suhwan Kim, Kosonocky, S.V., Knebel, D.R., Stawiasz, K., Heidel, D., Immediato, M.

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  8. 8
    A continuous density neural tree network word spotting system

    A continuous density neural tree network word spotting system by Kosonocky, S.V., Mammone, R.J.

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  9. 9
    Scalability options for future SRAM memories

    Scalability options for future SRAM memories by Kosonocky, S.V., Bhavnagarwala, A., Chang, L.

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  10. 10
    Multi-Dimensional Circuit and Micro-Architecture Level Optimization

    Multi-Dimensional Circuit and Micro-Architecture Level Optimization by Zhenyu Qi, Ziegler, M., Kosonocky, S.V., Rabaey, J.M., Stan, M.R.

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  11. 11
    Enhanced multi-threshold (MTCMOS) circuits using variable well bias

    Enhanced multi-threshold (MTCMOS) circuits using variable well bias by Kosonocky, S.V., Irnmediato, M., Cottrell, P., Hook, T., Mann, R., Brown, J.

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  12. 12
    Designing a testable system on a chip

    Designing a testable system on a chip by Kosonocky, S.V., Bright, A., Warren, K., Haring, R.A., Klepner, S., Asaad, S., Basavaiah, S., Havreluk, B., Heidel, D., Immediato, M., Jenkin, K., Joshi, R., Parker, B., Rajeevakumar, T.V., Stawiasz, K.

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