Search Results - Kunz, V.D.

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  1. 1
    Design of 50-nm vertical MOSFET incorporating a dielectric pocket

    Design of 50-nm vertical MOSFET incorporating a dielectric pocket by Donaghy, D., Hall, S., de Groot, C.H., Kunz, V.D., Ashburn, P.

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  2. 2
    Asymmetric gate-induced drain leakage and body leakage in vertical MOSFETs with reduced parasitic capacitance

    Asymmetric gate-induced drain leakage and body leakage in vertical MOSFETs with reduced parasitic capacitance by Gili, E., Kunz, V.D., Uchino, T., Hakim, M.M.A., de Groot, C.H., Ashburn, P., Hall, S.

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  3. 3
    Reduction of parasitic capacitance in vertical MOSFETs by spacer local oxidation

    Reduction of parasitic capacitance in vertical MOSFETs by spacer local oxidation by Kunz, V.D., Uchino, T., de Groot, C.H., Ashburn, P., Donaghy, D.C., Hall, S., Yun Wang, Hemment, P.L.F.

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  4. 4
    Polycrystalline silicon-germanium emitters for gain control, with application to SiGe HBTs

    Polycrystalline silicon-germanium emitters for gain control, with application to SiGe HBTs by Kunz, V.D., de Groot, C.H., Hall, S., Ashburn, P.

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  5. 5
    Single, double and surround gate vertical MOSFETs with reduced parasitic capacitance

    Single, double and surround gate vertical MOSFETs with reduced parasitic capacitance by Gili, E., Kunz, V.D., de Groot, C.H., Uchino, T., Ashburn, P., Donaghy, D.C., Hall, S., Wang, Y., Hemment, P.L.F.

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  6. 6
    Recent developments in deca-nanometer vertical MOSFETs

    Recent developments in deca-nanometer vertical MOSFETs by Hall, S, Donaghy, D, Buiu, O, Gili, E, Uchino, T, Kunz, V.D, de Groot, C.H, Ashburn, P

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  7. 7
    Electrical characteristics of single, double & surround gate vertical MOSFETs with reduced overlap capacitance

    Electrical characteristics of single, double & surround gate vertical MOSFETs with reduced overlap capacitance by Gili, E., Kunz, V.D., de Groot, C.H., Uchino, T., Donaghy, D., Hall, S., Ashburn, P.

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  8. 8
    A 50nm channel vertical MOSFET concept incorporating a retrograde channel and a dielectric pocket

    A 50nm channel vertical MOSFET concept incorporating a retrograde channel and a dielectric pocket by Lamb, A.C., Riley, L.S., Hall, S., Kunz, V.D., de Groot, C.H., Ashburn, P.

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  9. 9
    Application of Polycrystalline SiGe for Gain Control in SiGe Heterojunction Bipolar Transistors

    Application of Polycrystalline SiGe for Gain Control in SiGe Heterojunction Bipolar Transistors by Kunz, V.D., de Groot, C.H., Hall, S., Anteney, I.M., Abdul-Rahim, A.I., Ashburn, P.

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