The impacts of control gate voltage on the cycling endurance of split gate flash memory by Kuo-Ching Huang, Yean-Kuen Fang, Dun-Nian Yang, Chii-Wen Chen, Hung-Cheng Sung, Di-Son Kuo, Wang, C.S., Mong-Song Liang

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Effect of substrate bias on the performance and reliability of the split-gate source-side injected flash memory by Kuo-Ching Huang, Yean-Kuen Fang, Dun-Nian Yaung, Chii-Wen Chen, Hung-Cheng Sung, Di-Son Kuo, Wang, C.S., Mong-Song Liang

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Optimization of epitaxial layers for power bipolar-MOS transistor by Kuo, Di-Son, Hu, Chenming

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A novel programming technique for highly scalable and disturbance immune flash EEPROM by Huang, Kuo-Ching, Fang, Yean-Kuen, Yaung, Dun-Nian, Chen, Chung-Hui, Hsu, Yung-Lung, Ting, Shyh-Fann, Lin, Yvonne, Kuo, Di-son, Wang, Chung S., Liang, Mong-Song

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A flash-based SOC technology using a split-gate cell by Kuo, Di-Son, Wang, Chung, Chu, Sam, Liang, M.S, Tsai, C.S, Tao, H.J, Huang, Y.C, Wu, J.P, Chen, Y.T, Chih, Y.D, Hsieh, C.H, Sung, H.C, Yeh, J.K, Lin, C.J, Wong, S.C, Lin, S.H, Hsieh, C.T, Chu, W.T, Chen, H.P, Hsu, C.Y, Shyu, D.S, Peng, S.P, Fong, T.J, Lee, K.Y

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An analytical model for the power bipolar-MOS transistor by Kuo, Di-Son, Hu, Chenming, Sapp, Steven P.

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TEFET - a high density, low erase voltage, trench flash EEPROM by Kuo, Di-Son, Simpson, Mark, Tsou, Len, Mukherjee, Satyen

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Speed-Conductance Optimization for Power Bipolar-MOS Transistor by Kuo, Di-Son, Hu, Chenming

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TEFET-a high density, low erase voltage, trench flash EEPROM by Di-Son Kuo, Simpson, M., Tsou, L., Mukherjee, S.

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Optimization of epitaxial layers for power bipolar-MOS transistor by DI-SON KUO, CHENMING HU

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