Search Results - L'Insalata, N.E.

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  1. 1
    Low-Complexity Link Microarchitecture for Mesochronous Communication in Networks-on-Chip

    Low-Complexity Link Microarchitecture for Mesochronous Communication in Networks-on-Chip by Vitullo, F., L'Insalata, N.E., Petri, E., Saponara, S., Fanucci, L., Casula, M., Locatelli, R., Coppola, M.

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  2. 2
    Low Complexity LDPC Code Decoders for Next Generation Standards

    Low Complexity LDPC Code Decoders for Next Generation Standards by Brack, T., Alles, M., Lehnigk-Emden, T., Kienle, F., Wehn, N., L'Insalata, N.E., Rossi, F., Rovini, M., Fanucci, L.

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  3. 3
    VLSI design of a high-throughput multi-rate decoder for structured LDPC codes

    VLSI design of a high-throughput multi-rate decoder for structured LDPC codes by Rovini, M., L'Insalata, N.E., Rossi, F., Fanucci, L.

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    Hardware/Software FPGA-based Network Emulator for High-speed On-board Communications

    Hardware/Software FPGA-based Network Emulator for High-speed On-board Communications by Saponara, S., L'Insalata, N.E., Bacchillone, T., Petri, E., Del Corona, I., Fanucci, L.

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  5. 5
    A mesochronous physical link architecture for network-on-chip interconnects

    A mesochronous physical link architecture for network-on-chip interconnects by Vitullo, F., L'Insalata, N.E., Petri, E., Casula, M., Saponara, S., Fanucci, L., Locatelli, R., Coppola, M.

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