MAPS: Mapping Concurrent Dataflow Applications to Heterogeneous MPSoCs by Castrillon, J., Leupers, R., Ascheid, G.

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ConvAix: An Application-Specific Instruction-Set Processor for the Efficient Acceleration of CNNs by Bytyn, Andreas, Leupers, Rainer, Ascheid, Gerd

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AMAIX In-Depth: A Generic Analytical Model for Deep Learning Accelerators by Zurstraßen, Niko, Jünger, Lukas, Kogel, Tim, Keding, Holger, Leupers, Rainer

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Accelerating Deep Learning Inference in Constrained Embedded Devices Using Hardware Loops and a Dot Product Unit by Vreca, Jure, Sturm, Karl J. X., Gungl, Ernest, Merchant, Farhad, Bientinesi, Paolo, Leupers, Rainer, Brezocnik, Zmago

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Density-Based Statistical Clustering: Enabling Sidefire Ultrasonic Traffic Sensing in Smart Cities by Ascheid, Gerd, Leupers, Rainer, Raschen, Matthias, Gehring, Michael, Baag, Thomas, Schreier, Julien, Voss, Nils, Lücken, Volker, Lanius, Christian

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Deceptive Logic Locking for Hardware Integrity Protection Against Machine Learning Attacks by Sisejkovic, Dominik, Merchant, Farhad, Reimann, Lennart M., Leupers, Rainer

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Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach by Sisejkovic, Dominik, Merchant, Farhad, Reimann, Lennart M., Srivastava, Harshit, Hallawa, Ahmed, Leupers, Rainer

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Parameterized Posit Arithmetic Hardware Generator by Chaurasiya, Rohit, Gustafson, John, Shrestha, Rahul, Neudorfer, Jonathan, Nambiar, Sangeeth, Niyogi, Kaustav, Merchant, Farhad, Leupers, Rainer

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ProMiSE: A Programmable Hardware Monitor for Secure Execution in Zero Trust Networks by Singh, Nikhilesh, Pal, Shagnik, Leupers, Rainer, Merchant, Farhad, Rebeiro, Chester

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A Scalable, Multimode SVD Precoding ASIC Based on the Cyclic Jacobi Method by Guenther, Daniel, Leupers, Rainer, Ascheid, Gerd

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Technology Transfer in computing systems: The TETRACOM approach by Leupers, Rainer

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The art of temporal decoupling by Zurstraßen, Niko, Brandhofer, Ruben, Cubero-Cascante, José, Bosbach, Nils, Jünger, Lukas, Leupers, Rainer

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veriSIMPLER: An Automated Formal Verification Methodology for SIMPLER MAGIC Design Style Based In-Memory Computing by Jha, Chandan Kumar, Qayyum, Khushboo, Caglar Coskun, Kemal, Singh, Simranjeet, Hassan, Muhammad, Leupers, Rainer, Merchant, Farhad, Drechsler, Rolf

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Reducing idle time in event-triggered software execution via runnable migration and DPM-Aware scheduling by Copic, Milan, Leupers, Rainer, Ascheid, Gerd

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It's Getting Hot in Here: Hardware Security Implications of Thermal Crosstalk on ReRAMs by Staudigl, Felix, Al Indari, Hazem, Schon, Daniel, Chen, Hsin-Yu, Sisejkovic, Dominik, Joseph, Jan Moritz, Rana, Vikas, Menzel, Stephan, Hagelauer, Amelie, Leupers, Rainer

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Efficiency Enablers of Lightweight SDR for MIMO Baseband Processing by Guenther, Daniel, Leupers, Rainer, Ascheid, Gerd

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Work-in-Progress: A Universal Instrumentation Platform for Non-Volatile Memories by Staudigl, Felix, Hossein, Mohammed, Ziegler, Tobias, Indari, Hazem Al, Pelke, Rebecca, Siegel, Sebastian, Wouters, Dirk J., Sisejkovic, Dominik, Joseph Rainer Leupers, Jan Moritz

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Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms by Castrillon, Jeronimo, Velasquez, Ricardo, Stulova, Anastasia, Weihua Sheng, Jianjiang Ceng, Leupers, Rainer, Ascheid, Gerd, Meyr, Heinrich

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CLARINET: A quire-enabled RISC-V-based framework for posit arithmetic empiricism by Sharma, Niraj N., Jain, Riya, Pokkuluri, Mohana Madhumita, Patkar, Sachin B., Leupers, Rainer, Nikhil, Rishiyur S., Merchant, Farhad

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An Investigation on Inherent Robustness of Posit Data Representation by Alouani, Ihsen, Ben Khalifa, Anouar, Merchant, Farhad, Leupers, Rainer

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