Search Results - Lai, Jenn-Shiang

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  1. 1
    BIST-Assisted Tuning Scheme for Minimizing IO-Channel Power of TSV-Based 3D DRAMs

    BIST-Assisted Tuning Scheme for Minimizing IO-Channel Power of TSV-Based 3D DRAMs by Yun-Chao Yu, Chi-Chun Yang, Jin-Fu Li, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu

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  2. 2
    A channel-sharable built-in self-test scheme for multi-channel DRAMs

    A channel-sharable built-in self-test scheme for multi-channel DRAMs by Wu, Kuan-Te, Li, Jin-Fu, Lo, Chih-Yen, Lai, Jenn-Shiang, Kwai, Ding-Ming, Chou, Yung-Fa

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  3. 3
    23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache

    23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache by Ting, Tah-Kang Joseph, Gyh-Bin Wang, Ming-Hung Wang, Chun-Peng Wu, Chun-Kai Wang, Chun-Wei Lo, Li-Chin Tien, Der-Min Yuan, Yung-Ching Hsieh, Jenn-Shiang Lai, Wen-Pin Hsu, Chien-Chih Huang, Chi-Kang Chen, Yung-Fa Chou, Ding-Ming Kwai, Zhe Wang, Wei Wu, Tomishima, Shigeki, Stolt, Pat, Shih-Lien Lu

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  4. 4
    Neural networks for optimization problems in graph theory

    Neural networks for optimization problems in graph theory by Jenn-Shiang Lai, Sy-Yen Kuo, Ing-Yi Chen

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