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MOSFET effective channel length, threshold voltage, and series resistance determination by robust optimization
by
McAndrew, C.C.
,
Layman, P.A.
Published in
IEEE transactions on electron devices
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A compact thermal noise model for the investigation of soft error rates in MOS VLSI digital circuits
by
Layman, P.A.
,
Chamberlain, S.G.
Published in
IEEE journal of solid-state circuits
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Modeling and characterization of MOSFET width dependencies
by
Ashton, R.A.
,
Layman, P.A.
,
McAndrew, C.C.
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Accurate characterization of MOSFET overlap/fringing capacitance for circuit design
by
McAndrew, C.C.
,
Zaneski, G.
,
Layman, P.A.
,
Ayyar, S.G.
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A computationally efficient technique to extract diffused profiles and three dimensional collector resistances of high energy implanted bipolar devices
by
Chaudhry, S.
,
Chyan, Y.F.
,
Carroll, M.S.
,
Chen, A.S.
,
Nagy, W.J.
,
Lee, J.L.
,
Layman, P.A.
,
Stevie, F.A.
,
Rafferty, C.S.
,
Vuong, H.H.
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High performance 3.3 and 5 volt 0.5-/spl mu/m CMOS technologies for ASICs
by
Kizilyalli, I.C.
,
Thoma, M.J.
,
Lytle, S.A.
,
Martin, E.P.
,
Vitkavage, S.C.
,
Singh, R.
,
Bechtold, P.F.
,
Kearney, J.W.
,
Rambaud, M.
,
Oates, A.
,
Ryan, V.
,
Layman, P.A.
,
Twiford, M.
,
Cochran, W.T.
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Ieee Journal Of Solid-State Circuits
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Ieee Transactions On Electron Devices
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Engineering
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