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A 16K E/SUP 2/PROM employing new array architecture and designed-in reliability features
by
Yaron, G.
,
Prasad, S.J.
,
Ebel, M.S.
,
Leong, B.M.K.
Published in
IEEE journal of solid-state circuits
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Ieee Journal Of Solid-State Circuits
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Charge Carrier Processes
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Electron Traps
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Isolation Technology
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Nonvolatile Memory
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Prom
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