Search Results - Leveugle, A

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  1. 1
    Preoperative computed tomography, surgical treatment and long-term outcomes of dogs with abscesses on migrating vegetal foreign bodies and oropharyngeal stick injuries: 39 cases (2010-2021)

    Preoperative computed tomography, surgical treatment and long-term outcomes of dogs with abscesses on migrating vegetal foreign bodies and oropharyngeal stick injuries: 39 cases (2... by Manzoni, S, Santos, M, Leveugle, A, Dekerle, B, Garnier, P, Maurice, E, Decambron, A, Mortier, J, Manassero, M, Viateau, V

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  2. 2
    Guest Editorial

    Guest Editorial by Cecilia Metra, Régis Leveugle

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  3. 3
    Scan design and secure chip [secure IC testing]

    Scan design and secure chip [secure IC testing] by Hely, D., Flottes, M.-L., Bancel, F., Rouzeyre, B., Berard, N., Renovell, M.

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  4. 4
    On the evaluation of SEU sensitiveness in SRAM-based FPGAs

    On the evaluation of SEU sensitiveness in SRAM-based FPGAs by Bernardi, P., Reorda, M.S., Sterpone, L., Violante, M.

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  5. 5
    Scrubbing away transients and jiggling around the permanent: long survival of FPGA systems through evolutionary self-repair

    Scrubbing away transients and jiggling around the permanent: long survival of FPGA systems through evolutionary self-repair by Garvie, M., Thompson, A.

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  6. 6
    Asynchronous circuits sensitivity to fault injection

    Asynchronous circuits sensitivity to fault injection by Monnet, Y., Renaudin, M., Leveugle, R.

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  7. 7
    Hybrid soft error detection by means of infrastructure IP cores [SoC implementation]

    Hybrid soft error detection by means of infrastructure IP cores [SoC implementation] by Bolzani, L., Rebaudengo, M., Reorda, M.S., Vargas, F., Violante, M.

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  8. 8
    New high speed CMOS self-checking voter

    New high speed CMOS self-checking voter by Cazeaux, J.M., Rossi, D., Metra, C.

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  9. 9
    On combining fault classification and error propagation analysis in RT-Level dependability evaluation

    On combining fault classification and error propagation analysis in RT-Level dependability evaluation by Ammari, A., Hadjiat, K., Leveugle, R.

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  10. 10
    BIST of delay faults in the logic architecture of symmetrical FPGAs

    BIST of delay faults in the logic architecture of symmetrical FPGAs by Girard, P., Heron, O., Pravossoudovitch, S., Renovell, M.

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  11. 11
    Self-checking code-disjoint carry-select adder with low area overhead by use of add1-circuits

    Self-checking code-disjoint carry-select adder with low area overhead by use of add1-circuits by Ocheretnij, V., Marienfeld, D., Sogomonyan, E.S., Gossel, M.

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  12. 12
    Fault tolerant mechatronics [automotive applications]

    Fault tolerant mechatronics [automotive applications] by Dilger, E., Karrelmeyer, R., Straube, B.

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  13. 13
    A novel fault tolerant cache to improve yield in nanometer technologies

    A novel fault tolerant cache to improve yield in nanometer technologies by Agarwal, A., Paul, B.C., Roy, K.

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  14. 14
    Impact of ECCs on simultaneously switching output noise for on-chip busses of high reliability systems [error correcting codes]

    Impact of ECCs on simultaneously switching output noise for on-chip busses of high reliability systems [error correcting codes] by Rossi, D., Muccio, A., Nieuwland, A.K., Katoch, A., Metra, C.

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  15. 15
    Modeling and simulation of time domain faults in digital systems

    Modeling and simulation of time domain faults in digital systems by Junior, D.B., Vargas, F., Santos, M.B., Teixeira, I.C., Teixeira, J.P.

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  16. 16
    A hierarchical self test scheme for SoCs

    A hierarchical self test scheme for SoCs by Kretzschmar, C., Galke, C., Vierhaus, H.T.

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  17. 17
    Sizing CMOS circuits for increased transient error tolerance

    Sizing CMOS circuits for increased transient error tolerance by Dhillon, Y.S., Diril, A.U., Chatterjee, A., Singh, A.D.

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  18. 18
    Concurrent error detection in sequential circuits implemented using FPGAs with embedded memory blocks

    Concurrent error detection in sequential circuits implemented using FPGAs with embedded memory blocks by Krasniewski, A.

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  19. 19
    Experimental evaluation of master/checker architecture using power supply-and software-based fault injection

    Experimental evaluation of master/checker architecture using power supply-and software-based fault injection by Rajabzadeh, A., Miremadi, S.G., Mohandespour, M.

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  20. 20
    Low-area on-chip circuit for jitter measurement in a phase-locked loop

    Low-area on-chip circuit for jitter measurement in a phase-locked loop by Cazeaux, J.M., Omana, M., Metra, C.

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