Search Results - Lien, N.Z.

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  1. 1
    A novel junction-free BE-SONOS NAND flash

    A novel junction-free BE-SONOS NAND flash by Hang Ting Lue, Erh Kun Lai, Hsiao, Y.H., Hong, S.P., Wu, M.T., Hsu, F.H., Lien, N.Z., Wang, S.Y., Yang, L.W., Yang, T., Chen, K.C., Hsieh, K.Y., Liu, R., Chih Yuan Lu

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  2. 2
    A novel buried-channel FinFET BE-SONOS NAND Flash with improved memory window and cycling endurance

    A novel buried-channel FinFET BE-SONOS NAND Flash with improved memory window and cycling endurance by Hang-Ting Lue, Yi-Hsuan Hsiao, Pei-Ying Du, Sheng-Chih Lai, Tzu-Hsuan Hsu, Hong, S.P., Wu, M.T., Hsu, F.H., Lien, N.Z., Chi-Pin Lu, Jung-Yu Hsieh, Ling-Wu Yang, Tahone Yang, Kuang-Chao Chen, Kuang-Yeu Hsieh, Liu, R., Chih-Yuan Lu

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  3. 3
    Scaling evaluation of BE-SONOS NAND flash beyond 20 nm

    Scaling evaluation of BE-SONOS NAND flash beyond 20 nm by Hang-Ting Lue, Tzu-Hsuan Hsu, Lai, S.C., Hsiao, Y.H., Peng, W.C., Liao, C.W., Huang, Y.F., Hong, S.P., Wu, M.T., Hsu, F.H., Lien, N.Z., Wang, S.Y., Yang, L.W., Yang, T., Chen, K.C., Hsieh, K.Y., Rich Liu, Chih-Yuan Lu

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  4. 4
    Study of sub-30nm thin film transistor (TFT) charge-trapping (CT) devices for 3D NAND flash application

    Study of sub-30nm thin film transistor (TFT) charge-trapping (CT) devices for 3D NAND flash application by Tzu-Hsuan Hsu, Hang-Ting Lue, Chih-Chang Hsieh, Erh-Kun Lai, Chi-Pin Lu, Shih-Ping Hong, Ming-Tsung Wu, Hsu, F.H., Lien, N.Z., Jung-Yu Hsieh, Ling-Wu Yang, Tahone Yang, Kuang-Chao Chen, Kuang-Yeu Hsieh, Liu, R., Chih-Yuan Lu

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  5. 5
    Understanding STI edge fringing field effect on the scaling of charge-trapping (CT) NAND Flash and modeling of incremental step pulse programming (ISPP)

    Understanding STI edge fringing field effect on the scaling of charge-trapping (CT) NAND Flash and modeling of incremental step pulse programming (ISPP) by Hang-Ting Lue, Tzu-Hsuan Hsu, Yi-Hsuan Hsiao, Sheng-Chih Lai, Erh-Kun Lai, Shih-Ping Hong, Ming-Tsung Wu, Hsu, F.H., Lien, N.Z., Chi-Pin Lu, Szu-Yu Wang, Jung-Yu Hsieh, Ling-Wu Yang, Tahone Yang, Kuang-Chao Chen, Kuang-Yeu Hsieh, Liu, R., Chih-Yuan Lu

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  6. 6
    A novel planar floating-gate (FG) / charge-trapping (CT) NAND device using BE-SONOS inter-poly dielectric (IPD)

    A novel planar floating-gate (FG) / charge-trapping (CT) NAND device using BE-SONOS inter-poly dielectric (IPD) by Hang-Ting Lue, Pei-Ying Du, Tzu-Hsuan Hsu, Yi-Hsuan Hsiao, Sheng-Chih Lai, Szu-Yu Wang, Shih-Ping Hong, Ming-Tsung Wu, Hsu, F.H., Lien, N.Z., Chi-Pin Lu, Jung-Yu Hsieh, Ling-Wu Yang, Tahone Yang, Kuang-Chao Chen, Kuang-Yeu Hsieh, Liu, R., Chih-Yuan Lu

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