Search Results - Lien-Fei Chen

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  1. 1
    A high-performance and memory-efficient VLSI architecture with parallel scanning method for 2-D lifting-based discrete wavelet transform

    A high-performance and memory-efficient VLSI architecture with parallel scanning method for 2-D lifting-based discrete wavelet transform by Lai, Yeong-Kang, Chen, Lien-Fei, Shih, Yui-Chih

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  2. 2
    A 0.5 nJ/Pixel 4 K H.265/HEVC Codec LSI for Multi-Format Smartphone Applications

    A 0.5 nJ/Pixel 4 K H.265/HEVC Codec LSI for Multi-Format Smartphone Applications by Ju, Chi-Cheng, Liu, Tsu-Ming, Lee, Kun-Bin, Chang, Yung-Chang, Chou, Han-Liang, Wang, Chih-Ming, Wu, Tung-Hsing, Lin, Hue-Min, Huang, Yi-Hsin, Cheng, Chia-Yun, Lin, Ting-An, Chen, Chun-Chia, Lin, Yu-Kun, Chiu, Min-Hao, Li, Wei-Cing, Wang, Sheng-Jen, Lai, Yen-Chieh, Chao, Ping, Chien, Chih-Da, Hu, Meng-Jye, Wang, Peng-Hao, Huang, Yen-Chao, Chuang, Shun-Hsiang, Chen, Lien-Fei, Lin, Hsiu-Yi, Wu, Ming-Long, Chen, Che-Hong

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  3. 3
    Hybrid parallel motion estimation architecture based on fast top-winners search algorithm

    Hybrid parallel motion estimation architecture based on fast top-winners search algorithm by Lai, Yeong-kang, Chen, Lien-fei, Huang, Shien-yu

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  4. 4
    A memory interleaving and interlacing architecture for deblocking filter in H.264/AVC

    A memory interleaving and interlacing architecture for deblocking filter in H.264/AVC by Lai, Yeong-Kang, Chen, Lien-Fei, Chiou, Wei-Che

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  5. 5
    A high-speed 2-D transform architecture with unique kernel for multi-standard video applications

    A high-speed 2-D transform architecture with unique kernel for multi-standard video applications by Huang, Chong-Yu, Chen, Lien-Fei, Lai, Yeong-Kang

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  6. 6
    Scalable Motion Estimation Processor Core for Multimedia System-on-Chip Applications

    Scalable Motion Estimation Processor Core for Multimedia System-on-Chip Applications by Lai, Yeong-Kang, Hsieh, Tian-En, Chen, Lien-Fei

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  7. 7
    Model-based early termination scheme for H.264/AVC inter prediction

    Model-based early termination scheme for H.264/AVC inter prediction by Lien-Fei Chen, Shin-Ping Yang, Yeong-Kang Lai

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  8. 8
    High-Throughput Configurable Motion Estimation Processor Core for Video Applications

    High-Throughput Configurable Motion Estimation Processor Core for Video Applications by Lai, Yeong-Kang, Chen, Lien-Fei

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  9. 9
    A Reconfigurable Computing Processor Core for Multimedia System-on-Chip Applications

    A Reconfigurable Computing Processor Core for Multimedia System-on-Chip Applications by Lai, Yeong-Kang, Chen, Lien-Fei, Chen, Jian-Chou

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  10. 10
    Hardware efficient coarse-to-fine fast algorithm for H.264/AVC variable block size motion estimation

    Hardware efficient coarse-to-fine fast algorithm for H.264/AVC variable block size motion estimation by Lien-Fei Chen, Shien-Yu Huang, Chi-Yao Liao, Yeong-Kang Lai

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  11. 11
    A defect-tolerant reconfigurable nanoarchitecture design for multimedia applications

    A defect-tolerant reconfigurable nanoarchitecture design for multimedia applications by Lai, Yeong-Kang, Chen, Lien-Fei

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  12. 12
    18.6 A 0.5nJ/pixel 4K H.265/HEVC codec LSI for multi-format smartphone applications

    18.6 A 0.5nJ/pixel 4K H.265/HEVC codec LSI for multi-format smartphone applications by Ju, Chi-Cheng, Liu, Tsu-Ming, Lee, Kun-Bin, Chang, Yung-Chang, Chou, Han-Liang, Wang, Chin-Ming, Wu, Tung-Hsing, Lin, Hue-Min, Huang, Yi-Hsin, Cheng, Chia-Yun, Lin, Ting-An, Chen, Chun-Chia, Lin, Yu-Kun, Chiu, Min-Hao, Li, Wei-Cing, Wang, Sheng-Jen, Lai, Yen-Chieh, Chao, Ping, Chien, Chih-Da, Hu, Meng-Jye, Wang, Peng-Hao, Yeh, Fu-Chun, Huang, Yen-Chao, Chuang, Shun-Hsiang, Chen, Lien-Fei, Lin, Hsiu-Yi, Wu, Ming-Long, Chen, Che-Hong, Chen, Ryan, Hsu, H Y, Jou, Kevin

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  13. 13
    System anlaysis of power-aware H.264/AVC encoder based on fast inter prediction

    System anlaysis of power-aware H.264/AVC encoder based on fast inter prediction by Yeong-Kang Lai, Lien-Fei Chen, Shin-Ping Yang

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  14. 14
    Memory analysis and throughput enhancement for cost effective bit-plane coder in JPEG2000 applications

    Memory analysis and throughput enhancement for cost effective bit-plane coder in JPEG2000 applications by Lien-Fei Chen, Tai-Lun Huang, Yeong-Kang Lai

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  15. 15
    Analysis and architecture design of multi-transform architecture for H.264/AVC intra frame coder

    Analysis and architecture design of multi-transform architecture for H.264/AVC intra frame coder by Lien-Fei Chen, Kun-Hsing Li, Chong-Yu Huang, Yeong-Kang Lai

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  16. 16
    Hybrid parallel motion estimation architecture based on fast Pel-subsampling algorithm

    Hybrid parallel motion estimation architecture based on fast Pel-subsampling algorithm by Yeong-Kang Lai, Lien-Fei Chen, Tian-En Hsieh, Shien-Yu Huang

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  17. 17
    A two-way SIMD-based reconfigurable computing architecture for multimedia applications

    A two-way SIMD-based reconfigurable computing architecture for multimedia applications by Yeong-Kang Lai, Lien-Fei Chen, Jian-Chou Chen, Chun-Wei Chiu

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  18. 18
    Analysis and Architecture Design for Memory Efficient Parallel Embedded Block Coding Architecture in JPEG 2000

    Analysis and Architecture Design for Memory Efficient Parallel Embedded Block Coding Architecture in JPEG 2000 by Lien-Fei Chen, Tai-Lun Huang, Tzau-Min Chou, Yeong-Kang Lai

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  19. 19
    Fast and high-accuracy design and implementation for home electronic weighing scale applications

    Fast and high-accuracy design and implementation for home electronic weighing scale applications by Yeong-Kang Lai, Adik Liu, Lien-Fei Chen

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  20. 20
    A high throughput and memory efficient EBCOT architecture for JPEG2000 in digital camera applications

    A high throughput and memory efficient EBCOT architecture for JPEG2000 in digital camera applications by Yeong-Kang Lai, Lien-Fei Chen, Tai-Lun Huang

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