Reliability of a Silicon Stacked Module for 3-D SiP Microsystem by Seung Wook Yoon, Lim, S.Y.L., Viswanath, A.G.K., Thew, S., Tai Chong Chai, Kripesh, V.

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Packaging and Assembly of 3-D Silicon Stacked Module for Image Sensor Application by Seung Wook Yoon, Ganesh, V.P., Lim, S.Y.L., Kripesh, V.

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150-[mu]m Pitch Cu/Low-k Flip Chip Packaging With Polymer Encapsulated Dicing Line (PEDL) and Cu Column Interconnects by Seung Wook Yoon, Seung Wook Yoon, Thew, S.M.L, Lim, S.Y.L, Wai Yin Hnin, Wai Yin Hnin, Tai Chong Chai, Tai Chong Chai, Viswanath, A.G.K, Kripesh, V

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Physical Mechanism of Interfacial Thermal Resistance in Electronic Packaging Based on a Mixed MD/FE Model by Yang, Ping, Liao, Ningbo

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150- \mu Pitch Cu/Low- Flip Chip Packaging With Polymer Encapsulated Dicing Line (PEDL) and Cu Column Interconnects by Seung Wook Yoon, Thew, S.M.L., Lim, S.Y.L., Wai Yin Hnin, Tai Chong Chai, Viswanath, A.G.K., Kripesh, V.

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Surface mountable low cost packaging for RFID device by Lim, S.Y.L., Ser Choong Chong, Lihui Guo, Wai Yin Hnin

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