Search Results - Lin, Ichiang

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  1. 1
    Timing Challenges for Very Deep Sub-Micron (VDSM) IC

    Timing Challenges for Very Deep Sub-Micron (VDSM) IC by Lin, Ichiang, Chen, Chien-In Henry

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  2. 2
    Timing verification of dynamic circuits

    Timing verification of dynamic circuits by Venkat, K., Liang Chen, Ichiang Lin, Mistry, P., Madhani, P.

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  3. 3
    On wafer-packing problems

    On wafer-packing problems by Du, D.H.C., Ichiang Lin, Chang, K.C.

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  4. 4
    Timing verification of dynamic circuits

    Timing verification of dynamic circuits by Venkat, Kumar, Chen, Liang, Lin, Ichiang, Mistry, Piyush, Madhani, Pravin, Sato, Katsuya

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  5. 5
    Gate Matrix Layout Synthesis with Two-Dimensional Folding

    Gate Matrix Layout Synthesis with Two-Dimensional Folding by Ichiang Lin, Du, D.H.C., Yen, S.H.C.

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  6. 6
    Analyzing cycle stealing on synchronous circuits with level-sensitive latches

    Analyzing cycle stealing on synchronous circuits with level-sensitive latches by Lin, I., Ludwig, J.A., Eng, K.

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  7. 7
    Gate matrix layout synthesis with two-dimensional folding

    Gate matrix layout synthesis with two-dimensional folding by Lin, I., Du, D. H. C., Yen, S. H. C.

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  8. 8
    Performance-driven constructive placement

    Performance-driven constructive placement by Lin, Ichiang, Du, David H. C.

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