Unleashing Parallelism With Minimal Test Inflation in Multi-Threaded Test Pattern Generation by Lin, Louis Y.-Z, Wen, Charles H.-P

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Fast Scan-Chain Ordering for 3-D-IC Designs Under Through-Silicon-Via (TSV) Constraints by Liao, C. C., Chen, A. W., Lin, L. Y., Wen, C. H.

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TA-FTA: Transition-aware functional timing analysis with a four-valued encoding by Chang, Jasper C. C., Huang, Ryan H.-M, Lin, Louis Y.-Z, Wen, Charles H.-P

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P4-TPG: Accelerating Deterministic Parallel Test Pattern Generation by Preemptive, Proactive, and Preventive Schedulings by Lin, Louis Y.-Z., Hsu, Charles Chia-Hao, Wen, Charles H.-P.

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Speed binning with high-quality structural patterns from functional timing analysis (FTA) by Lin, Louis Y.-Z, Wen, Charles H.-P

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Suppressing test inflation in shared-memory parallel Automatic Test Pattern Generation by Ku, Jerry C. Y., Huang, Ryan H-M, Lin, Louis Y-Z, Wen, Charles H-P

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Synthesizing multiple scan chains by cost-driven spectral ordering by Lin, L. Y-Z, Liao, C. C-H, Wen, C. H-P

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Benz[f]indene by Carpino, Louis A, Lin, Yao Zhong

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