Search Results - Liu, Shau-Shen

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  1. 1
    A compact LDD MOSFET I-V model based on nonpinned surface potential

    A compact LDD MOSFET I-V model based on nonpinned surface potential by Jang, Sheng-Lyang, Liu, Shau-Shen, Sheu, Chorng-Jye

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  2. 2
    New Submicron and Deep-Submicron Metal-Oxide-Semiconductor Field-Effect-Transistor I–V and C–V Model

    New Submicron and Deep-Submicron Metal-Oxide-Semiconductor Field-Effect-Transistor I–V and C–V Model by Jang, Sheng-Lyang, Liu, Shau-Shen

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  3. 3
    An analytical symmetric double-gate silicon-on-insulator metal-oxide-semiconductor field-effect-transistor model

    An analytical symmetric double-gate silicon-on-insulator metal-oxide-semiconductor field-effect-transistor model by JANG, S.-L, HU, M.-C, LIU, S.-S

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  4. 4
    A simple, analytical and complete deep-submicrometer fully depleted silicon-on-insulator metal-oxide-semiconductor field-effect-transistor model considering velocity overshoot

    A simple, analytical and complete deep-submicrometer fully depleted silicon-on-insulator metal-oxide-semiconductor field-effect-transistor model considering velocity overshoot by JANG, S.-L, HU, M.-C, LIU, S.-S, CHEN, Y.-S

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  5. 5
    An analytical fully-depleted silicon-on-insulator metal-oxide-semiconductor field-effect-transistor model considering the effects of self-heating, source/drain resistance, impact-ionization, and parasitic bipolar junction transistor

    An analytical fully-depleted silicon-on-insulator metal-oxide-semiconductor field-effect-transistor model considering the effects of self-heating, source/drain resistance, impact-i... by HU, M.-C, JANG, S.-L, CHEN, Y.-S, LIU, S.-S, LIN, J.-M

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  6. 6
    Deep-Submicron Lightly-Doped-Drain and Single-Drain Metal-Oxide-Semiconductor Transistor Drain Current Model for Circuit Simulation

    Deep-Submicron Lightly-Doped-Drain and Single-Drain Metal-Oxide-Semiconductor Transistor Drain Current Model for Circuit Simulation by Liu, Shau-Shen, Jang, Sheng-Lyang

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  7. 7
    A Compact Buried-Channel Lightly-Doped-Drain Metal-Oxide-Semiconductor- Field-Effect-Transistor Model

    A Compact Buried-Channel Lightly-Doped-Drain Metal-Oxide-Semiconductor- Field-Effect-Transistor Model by Jang, Sheng-Lyang, Chyau, Chwan-Gwo, Liu, Shau-Shen, Chiu, Chung-Ming

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  8. 8
    A New Post-stress Drain Current Model for Surface-channel p-Type Metal-Oxide-Semiconductor-Field-Effect-Transistors

    A New Post-stress Drain Current Model for Surface-channel p-Type Metal-Oxide-Semiconductor-Field-Effect-Transistors

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  9. 9
    A novel approach for modeling accumulation-mode SOI MOSFETs

    A novel approach for modeling accumulation-mode SOI MOSFETs by Jang, Sheng-Lyang, Liu, Shau-Shen

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  10. 10
    28.2: Development of a 312ppi 4.1-inch XGA Display with Low Temperature Poly-Si Technology

    28.2: Development of a 312ppi 4.1-inch XGA Display with Low Temperature Poly-Si Technology by Kung, Nien-Hui, Yeh, Yung-Hui, Chen, Chih-Chiang, Chang, Shang-Wen, Wang, Li-Wing, Wang, Bowen, Chen, Shang-Li, Chen, Pi-Fu, Kang, Yu-Ming, Liu, Shau-Shen

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  11. 11
    An analytical symmetric double-gate SOI MOSFET model

    An analytical symmetric double-gate SOI MOSFET model by JIOU, HONG-KEE, JANG, SHENG-LYANG, LIU, SHAU-SHEN

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  12. 12
    An analytical, physics-based linear current-voltage model for hot-carrier damaged LDD nMOSFETS

    An analytical, physics-based linear current-voltage model for hot-carrier damaged LDD nMOSFETS by Liu, Shau-Shen, Hu, Man-Chun, Jang, Sheng-Lyang

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  13. 13
    Compact LDD nMOSFET degradation model

    Compact LDD nMOSFET degradation model by Liu, S.-S., Jang, S.-L., Chyau, C.-G.

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