Nanoscale CMOS Implications on Analog/Mixed-Signal Design by Loke, Alvin L.S., Lee, C.K., Leary, B. Mike

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Design Challenges and Techniques for 5nm FinFET CMOS Analog/Mixed-Signal Circuits by Goyal, Saurabh, Wadhwa, Sanjay Kumar, Tripathi, Divya, Agrawal, Gaurav, Thakur, Krishna, Jain, Deependra Kumar, Loke, Alvin L.S., Kumar, Atul, Upadhyay, Manish Kumar, Bhawna, Dey, Sanjoy Kumar

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An 8.0-Gb/s HyperTransport Transceiver for 32-nm SOI-CMOS Server Processors by Loke, A. L. S., Doyle, B. A., Maheshwari, S. K., Fischette, D. M., Wang, C. L., Tin Tin Wee, Fang, E. S.

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A Versatile 90-nm CMOS Charge-Pump PLL for SerDes Transmitter Clocking by Loke, A.L.S., Barnes, R.K., Wee, T.T., Oshima, M.M., Moore, C.E., Kennedy, R.R., Gilsdorf, M.J.

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An Embedded All-Digital Circuit to Measure PLL Response by Fischette, Dennis M, Loke, Alvin L S, DeSantis, Richard J, Talbot, Gerry R

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Analog/Mixed-Signal Design Challenges in 7-nm CMOS and Beyond by Loke, Alvin L. S., Yang, Da, Wee, Tin Tin, Holland, Jonathan L., Isakanian, Patrick, Rim, Kern, Yang, Sam, Schneider, Jacob S., Nallapati, Giri, Dundigal, Sreeker, Lakdawala, Hasnain, Amelifard, Behnam, Lee, Chulkyu, McGovern, Betty, Holdaway, Paul S., Kong, Xiaohua, Leary, Burton M.

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Analog/mixed-signal design challenges in 7-nm CMOS and beyond by Loke, Alvin L. S., Yang, Da, Wee, Tin Tin, Holland, Jonathan L., Isakanian, Patrick, Rim, Kern, Yang, Sam, Schneider, Jacob S., Nallapati, Giri, Dundigal, Sreeker, Lakdawala, Hasnain, Amelifard, Behnam, Lee, Chulkyu, McGovern, Betty, Holdaway, Paul S., Kong, Xiaohua, Leary, Burton M.

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Microstructure and reliability of copper interconnects by Changsup Ryu, Kee-Won Kwon, Loke, A.L.S., Haebum Lee, Nogami, T., Dubin, V.M., Kavari, R.A., Ray, G.W., Wong, S.S.

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Kinetics of copper drift in PECVD dielectrics by Loke, A.L.S., Changsup Ryu, Yue, C.P., Cho, J.S.H., Wong, S.S.

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SIS wide-band model extraction methodology for SOI on-chip inductor by Topaloglu, Rasit Onur, Jung-Suk Goo, Loke, Alvin L S, Oshima, Michael M, Sim, Sam Wonsae

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A 4-to-18GHz Active Poly Phase Filter Quadrature Clock Generator with Phase Error Correction in 5nm CMOS by Chen, Wei-Chih, Wen, Chin-Hua, Fu, Chin-Ming, Tsai, Tsung-Hsien, Chen, Yu-Chi, Huang, Wen-Hung, Tsai, Chien-Chun, Loke, Alvin L. S., Kenny, C. H.

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Bridging design and manufacture of analog/mixed-signal circuits in advanced CMOS by Jia Feng, Loke, A. L. S., Tin Tin Wee, Lackey, C. O., Okada, L. A., Schwan, C. T., Mantei, T., Morgan, J. H., Herden, M. M., Cooper, J. G., Zhi-Yuan Wu, Jung-Suk Goo, Xin Li, Icel, A. B., Bair, L. A., Fischette, D. M., Doyle, B. A., Fang, E. S., Leary, B. M., Krishnan, S.

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Embedded PLL Phase Noise Measurement Based on a PFD/CP MASH 1-1-1 ΔΣ Time-to-Digital Converter in 7nm CMOS by Chou, Mao-Hsuan, Chang, Ya-Tin, Tsai, Tsung-Hsien, Lu, Tsung-Che, Liao, Chia-Chun, Kuo, Hung-Yi, Sheen, Ruey-Bin, Chang, Chih-Hsien, Hsieh, Kenny C. H., Loke, Alvin L. S., Chen, Mark

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HYDROGEN-ROBUST SUBMICRON IrOx/Pb(Zr, Ti)O3/Ir CAPACITORS FOR EMBEDDED FERROELECTRIC MEMORY by Sakoda, T, Moise, T S, Summerfelt, S R, Colombo, L, Xing, G, Gilbert, S R

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Electrical leakage at low-K polyimide/TEOS interface by Loke, A.L.S., Wetzel, J.T., Stankus, J.J., Angyal, M.S., Mowry, B.K., Wong, S.S.

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Barriers for copper interconnections by Ryu, Changsup, Lee, Haebum, Kwon, Kee-Won, Loke, Alvin L.S, Wong, S. Simon

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Extending HyperTransport™ technology to 8.0 Gb/s in 32-nm SOI-CMOS processors by Doyle, B. A., Loke, A. L. S., Maheshwari, S. K., Wang, C. L., Fischette, D. M., Cooper, J. G., Aggarwal, S. K., Wee, T. T., Lackey, C. O., Kedarnath, H. S., Oshima, M. M., Talbot, G. R., Fang, E. S.

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