Search Results - Lubaszewski, M S

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  1. 1
    Built-In Self-Test of Field Programmable Analog Arrays based on Transient Response Analysis

    Built-In Self-Test of Field Programmable Analog Arrays based on Transient Response Analysis by Balen, T R, Calvano, J V, Lubaszewski, M S, Renovell, M

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  2. 2
    TID in a Switched-Capacitor FPAA: Degradation and Partial Inactivity Windows Due to Compensating Effects in MOS Transistors

    TID in a Switched-Capacitor FPAA: Degradation and Partial Inactivity Windows Due to Compensating Effects in MOS Transistors by Balen, T. R., Vaz, R. G., Cardoso, G. S., Goncalez, O. L., Lubaszewski, M. S.

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  3. 3
    Low pin count DfT technique for RFID ICs

    Low pin count DfT technique for RFID ICs by de Souza Moraes, M., Herve, M. B., Lubaszewski, M. S.

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  4. 4
    Task mapping on NoC-based MPSoCs with faulty tiles: Evaluating the energy consumption and the application execution time

    Task mapping on NoC-based MPSoCs with faulty tiles: Evaluating the energy consumption and the application execution time by Amory, A. M., Marcon, C. A. M., Moraes, F. G., Lubaszewski, M. S.

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  5. 5
    Evaluating energy consumption of homogeneous MPSoCs using spare tiles

    Evaluating energy consumption of homogeneous MPSoCs using spare tiles by Amory, A M, Ost, L C, Marcon, César A M, Moraes, F G, Lubaszewski, M S

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  6. 6
    Functional test of field programmable analog arrays

    Functional test of field programmable analog arrays by Balen, T.R., Calvano, J.V., Lubaszewski, M.S., Renovelf, M.

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  7. 7
    Designing for test analog signal processors for MEMS-based inertial sensors

    Designing for test analog signal processors for MEMS-based inertial sensors by Calvano, J.V., Lubaszewski, M.S.

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  8. 8
    Fault Models and Compact Test Vectors for MOS OpAmp circuits

    Fault Models and Compact Test Vectors for MOS OpAmp circuits by Calvano, J. V., Alves, V. C., Lubaszewski, M. S., Mesquita, A. C.

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  9. 9
    Fault models and compact test vectors for MOS opamp circuits

    Fault models and compact test vectors for MOS opamp circuits by Calvano, J.V., Alves, V.C., Lubaszewski, M.S., Mesquita, A.C.

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  10. 10
    Investigating the effects of transient faults in Programmable Capacitor Arrays

    Investigating the effects of transient faults in Programmable Capacitor Arrays by Balen, T. R., Cardoso, G. S., Goncalez, O. L., Lubaszewski, M. S.

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  11. 11
    A low-voltage CMOS exponential function circuit for AGC applications

    A low-voltage CMOS exponential function circuit for AGC applications by Chi-Hung Lin, Pimenta, T.C., Ismail, M.

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  12. 12
    MorphoSys: a reconfigurable architecture for multimedia applications

    MorphoSys: a reconfigurable architecture for multimedia applications by Singh, H., Ming-Hau Lee, Guangming Lu, Kurdahi, F.J., Bagherzadeh, N., Filho, E.M.C.

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  13. 13
    Synthesis of CMOS operational amplifiers through genetic algorithms

    Synthesis of CMOS operational amplifiers through genetic algorithms by Zebulum, R.S., Pacheco, M.A., Vellasco, M.

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  14. 14
    Hardware-software codesign of embedded systems

    Hardware-software codesign of embedded systems by Coelho, C.J.N., Silva, D.C.D., Fernandes, A.O.

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  15. 15
    SRAM-based FPGAs: a structural test approach

    SRAM-based FPGAs: a structural test approach by Renovell, M.

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  16. 16
    A built-in multi-mode stimuli generator for analogue and mixed-signal testing

    A built-in multi-mode stimuli generator for analogue and mixed-signal testing by Lubaszewski, M., Renovell, M., Mir, S., Azais, F., Bertrand, Y.

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  17. 17
    A constraint management system for IC physical design

    A constraint management system for IC physical design by Malavasi, E., Charbon, E., Arsintescu, B., Kao, W.

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  18. 18
    Repeater and interconnect strategies for high-performance physical designs

    Repeater and interconnect strategies for high-performance physical designs by Muddu, S., Sarto, E., Hofmann, M., Bashteen, A.

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  19. 19
    Operation in space of artificial neural networks implemented by means of a dedicated architecture based on a transputer

    Operation in space of artificial neural networks implemented by means of a dedicated architecture based on a transputer by Velazco, R., Cheynet, Ph, Ecoffet, R.

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  20. 20
    Topological parameters for library free technology mapping

    Topological parameters for library free technology mapping by Reis, A., Robert, M., Reis, R.

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