Manufacturable Processes for < 32-nm-node CMOS Enhancement by Synchronous Optimization of Strain-Engineered Channel and External Parasitic Resistances by NOORI, Atif M, BALSEANU, Mihaela, LAUWERS, Anne, LEE, Wen-Chin, JIANXIN LEI, MANDREKAR, Tushar, SCHREUTELKAMP, Robert, SHAH, Kavita, THOMPSON, Scott E, VERHEYEN, Peter, WANG, Ching-Ya, XIA, Li-Qun, BOELEN, Pieter, ARGHAVANI, Reza, COCKBUM, Andrew, DEMUYNCK, Steven, FELCH, Susan, GANDIKOTA, Srinivas, JERRY GELATOS, A, KHANDELWAL, Amit, KITTL, Jorge A

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Ni based silicides for 45 nm CMOS and beyond by Lauwers, Anne, Kittl, Jorge A., Van Dal, Mark J.H., Chamirian, Oxana, Pawlak, Malgorzata A., de Potter, Muriel, Lindsay, Richard, Raymakers, Toon, Pages, Xavier, Mebarki, Bencherki, Mandrekar, Tushar, Maex, Karen

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Manufacturable Processes for \leq 32-nm-node CMOS Enhancement by Synchronous Optimization of Strain-Engineered Channel and External Parasitic Resistances by Noori, A.M., Balseanu, M., Boelen, P., Cockburn, A., Demuynck, S., Felch, S., Gandikota, S., Gelatos, A.J., Khandelwal, A., Kittl, J.A., Lauwers, A., Wen-Chin Lee, Jianxin Lei, Mandrekar, T., Schreutelkamp, R., Shah, K., Thompson, S.E., Verheyen, P., Ching-Ya Wang, Li-Qun Xia, Arghavani, R.

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Enabling Effective Work Function Tuning by RF-PVD Metal Oxide on High-k Gate Dielectric by Yoshida, Naomi, Tang, Xianmin, Ahmed, Khaled, Conti, Giuseppina, Liu, Dave, Agustin, Melody, Hung, Steven, Ku, Victor, Chan, Osbert, Liang, Robert, Chen, Hao, Wang, Rongjun, Zheng, Bo, Lazik, Christopher, Jin, Miao, Lavu, Kishore, Chang, Chorng-Ping, Mandrekar, Tushar, Gandikota, Srinivas

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Ni based silicides for 45nm CMOS and beyond by Lauwers, Anne, Kittl, Jorge A., Van Dal, Mark J.H., Chamirian, Oxana, Pawlak, Malgorzata A., de Potter, Muriel, Lindsay, Richard, Raymakers, Toon, Pages, Xavier, Mebarki, Bencherki, Mandrekar, Tushar, Maex, Karen

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