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An empirical three-dimensional crossover capacitance model for multilevel interconnect VLSI circuits
by
Wong, Shyh-Chyi
,
Lee, Trent Gwo-Yann
,
Ma, Dye-Junn
,
Chao, Chuan-Jane
Published in
IEEE transactions on semiconductor manufacturing
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Ieee Transactions On Semiconductor Manufacturing
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Capacitance
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Capacitance Measurement
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Chaos
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Closed-Form Models
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Crossover Capacitance
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Delay
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Engineering, Manufacturing
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Geometry
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Integrated Circuit Interconnections
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Integrated Circuits
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Multilevel Interconnects
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Physical Sciences
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