Pharmacokinetic interaction of intravenous fentanyl with ketoconazole by Ziesenitz, Victoria C., König, Sonja K., Mahlke, Nina S., Skopp, Gisela, Haefeli, Walter E., Mikus, Gerd

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SODA: A High-Performance DSP Architecture for Software-Defined Radio by Lin, Y., Lee, H., Woh, M., Harel, Y., Mahlke, S., Mudge, T., Chakrabarti, C., Flautner, K.

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Automated custom instruction generation for domain-specific processor acceleration by Clark, N.T., Zhong, H., Mahlke, S.A.

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Processor acceleration through automated instruction set customization by Clark, N., Hongtao Zhong, Mahlke, S.

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Application-Specific Processing on a General-Purpose Core via Transparent Instruction Set Customization by Clark, Nathan, Kudlur, Manjunath, Park, Hyunchul, Mahlke, Scott, Flautner, Krisztian

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Acute or chronic pulmonary emphysema? Or both?—A contribution to the diagnosis of death due to violent asphyxiation in cases with pre-existing chronic emphysema by Gava, Giuseppe, Eickhoff, Simon B., Filler, Timm J., Mayer, Felix, Mahlke, Nina S., Ritz-Timme, Stefanie

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The StageNet fabric for constructing resilient multicore systems by Gupta, Shantanu, Feng, Shuguang, Ansari, Amin, Blome, Jason, Mahlke, Scott

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BulletProof: a defect-tolerant CMP switch architecture by Constantinides, K., Plaza, S., Blome, J., Zhang, B., Bertacco, V., Mahlke, S., Austin, T., Orshansky, M.

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Bitwidth cognizant architecture synthesis of custom hardware accelerators by Mahlke, S., Ravindran, R., Schlansker, M., Schreiber, R., Sherwood, T.

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Mobile supercomputers by Austin, T., Blaauw, D., Mahlke, S., Mudge, T., Chakrabarti, C., Wolf, W.

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An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors by Clark, Nathan, Blome, Jason, Chu, Michael, Mahlke, Scott, Biles, Stuart, Flautner, Krisztian

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Reliability: Fallacy or Reality? by Gonzalez, A., Mahlke, S., Mukherjee, S., Sendag, R., Chiou, D., Yi, J.J.

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Validation of Nursing Nutrition Screening Tool in Adult Acute Inpatient Setting by Lengfelder, L., Lee, J., Ueckert, H., Connors, R., Mahlke, S., Martin, E., Wieser, J., Zhang, X., Thomas, L., Moore, J., McHenry, M., Williams, G.

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Composite Cores: Pushing Heterogeneity Into a Core by Lukefahr, A., Padmanabha, S., Das, R., Sleiman, F. M., Dreslinski, R., Wenisch, T. F., Mahlke, S.

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Uncovering hidden loop level parallelism in sequential applications by Hongtao Zhong, Mehrara, M., Lieberman, S., Mahlke, S.

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Partitioning variables across register windows to reduce spill code in a low-power processor by Ravindran, R.A., Senger, R.M., Marsman, E.D., Dasika, G.S., Guthaus, M.R., Mahlke, S.A., Brown, R.B.

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Eliminating Concurrency Bugs with Control Engineering by Kelly, T., Yin Wang, Lafortune, S., Mahlke, S.

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Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System by Fan, Kevin, Kudlur, Manjunath, Park, Hyunchul, Mahlke, Scott

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A distributed control path architecture for VLIW processors by Hongtao Zhong, Fan, K., Mahlke, S., Schlansker, M.

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Polymorphic pipeline array: a flexible multicore accelerator with virtualized execution for mobile multimedia applications by Park, Hyunchul, Park, Yongjun, Mahlke, Scott

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