Search Results - Majhi, Ananta K

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  1. 1
    NIM-X: A Noise Index Model-Based X-Filling Technique to Overcome the Power Supply Switching Noise Effects on Path Delay Test

    NIM-X: A Noise Index Model-Based X-Filling Technique to Overcome the Power Supply Switching Noise Effects on Path Delay Test by Alpaslan, E., Kruseman, B., Majhi, A. K., Heuvalman, W. M., Dworak, J.

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  2. 2
    On hazard-free patterns for fine-delay fault testing

    On hazard-free patterns for fine-delay fault testing by Kruseman, B., Majhi, A.K., Gronthoud, G., Eichenberger, S.

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  3. 3
    NIM- a noise index model to estimate delay discrepancies between silicon and simulation

    NIM- a noise index model to estimate delay discrepancies between silicon and simulation by Alpaslan, Elif, Dworak, Jennifer, Kruseman, Bram, Majhi, Ananta K, Heuvelman, Wilmar M, van de Wiel, Paul

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  4. 4
    Line coverage of path delay faults

    Line coverage of path delay faults by Majhi, A.K., Agrawak, V.D., Jacob, J., Patnaik, L.M.

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  5. 5
    New test methodology for resistive open defect detection in memory address decoders

    New test methodology for resistive open defect detection in memory address decoders by Azimane, M., Majhi, A.K.

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  6. 6
    Memory Testing Under Different Stress Conditions: An Industrial Evaluation

    Memory Testing Under Different Stress Conditions: An Industrial Evaluation by Majhi, Ananta K., Azimane, Mohamed, Gronthoud, Guido, Lousberg, Maurice, Eichenberger, Stefan, Bowen, Fred

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  7. 7
    A Novel Path Delay Fault Simulator Using Binary Logic

    A Novel Path Delay Fault Simulator Using Binary Logic by Majhi, Ananta K., Jacob, James, Patnaik, Lalit M.

    Published in VLSI Design
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  8. 8
    Efficient Grouping of Fail Chips for Volume Yield Diagnostics

    Efficient Grouping of Fail Chips for Volume Yield Diagnostics by Lavanya Jagan, Singh, R.D., Kamakoti, V., Majhi, A.K.

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  9. 9
    Impact of Temperature on Test Quality

    Impact of Temperature on Test Quality by Jagan, L., Hora, C., Kruseman, B., Eichenberger, S., Majhi, A.K., Kamakoti, V.

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  10. 10
    An efficient automatic test generation system for path delay faults in combinational circuits

    An efficient automatic test generation system for path delay faults in combinational circuits by Majhi, A.K., Jacob, J., Patnaik, L.M., Agrawal, V.D.

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  11. 11
    Memory Testing Under Different Stress Conditions: An Industrial Evaluation

    Memory Testing Under Different Stress Conditions: An Industrial Evaluation by Majhi, Ananta K, Azimane, Mohamed, Gronthoud, Guido, Lousberg, Maurice, Eichenberger, Stefan, Bowen, Fred

    Published in arXiv.org
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  12. 12
    A genetic algorithm-based circuit partitioner for MCMs

    A genetic algorithm-based circuit partitioner for MCMs by Majhi, Ananta K., Patnaik, L.M., Raman, Srilata

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