Reconfigurable Multifunctional van der Waals Ferroelectric Devices and Logic Circuits by Ram, Ankita, Maity, Krishna, Marchand, Cédric, Mahmoudi, Aymen, Kshirsagar, Aseem Rajan, Soliman, Mohamed, Taniguchi, Takashi, Watanabe, Kenji, Doudin, Bernard, Ouerghi, Abdelkarim, Reichardt, Sven, O’Connor, Ian, Dayen, Jean-Francois

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Implementation and Characterization of a Physical Unclonable Function for IoT: A Case Study With the TERO-PUF by Marchand, Cedric, Bossuet, Lilian, Mureddu, Ugo, Bochard, Nathalie, Cherkaoui, Abdelkarim, Fischer, Viktor

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Buffers optimization for multi-core decoders by Boutillon, Emmanuel, Marchand, Cedric

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The Best, the Requested, and the Default Elementary Check Node for EMS NB-LDPC Decoder by Jabour, Joseph, Marchand, Cedric, Boutillon, Emmanuel

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Ultra-High-Throughput EMS NB-LDPC Decoder with Full-Parallel Node Processing by Harb, Hassan, Ghouwayel, Ali Chamas Al, Conde-Canencia, Laura, Marchand, Cédric, Boutillon, Emmanuel

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Hybrid Check Node Architectures for NB-LDPC Decoders by Marchand, Cedric, Boutillon, Emmanuel, Harb, Hassan, Conde-Canencia, Laura, Al Ghouwayel, Ali

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Area‐oriented comparison of lightweight block ciphers implemented in hardware for the activation mechanism in the anti‐counterfeiting schemes by Marchand, Cédric, Bossuet, Lilian, Gaj, Kris

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Low-level implementation and side-channel detection of stealthy hardware trojans on field programmable gate arrays by Marchand, Cédric, Francq, Julien

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Identification of IP control units by state encoding and side channel verification by Jung, Edward, Bossuet, Lilian, Choi, Seonho, Marchand, Cédric

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Simplified Compression of Redundancy Free Trellis Sections in Turbo Decoder by Boutillon, Emmanuel, Sanchez-Rojas, Jose-Luis, Marchand, Cedric

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FVLLMONTI: The 3D Neural Network Compute Cube (N^C^) Concept for Efficient Transformer Architectures Towards Speech-to-Speech Translation by O'Connor, Ian, Mannaa, Sara, Bosio, Alberto, Deveautour, Bastien, Deleruyelle, Damien, Obukhova, Tetiana, Marchand, Cedric, Trommer, Jens, Cakirlar, Cigdem, Wesling, Bruno Neckel, Mikolajick, Thomas, Baumgartner, Oskar, Thesberg, Mischa, Pirker, David, Lenz, Christoph, Stanojevic, Zlatan, Karner, Markus, Larrieu, Guilhem, Pelloquin, Sylvain, Moustakas, Konstantinous, Muller, Jonas, Ansaloni, Giovanni, Amirshahi, Alireza, Atienza, David, Rouas, Jean-Luc, Letaifa, Leila Ben, Bordeall, Georgeta, Brazier, Charles, Mukherjee, Chhandak, Deng, Marina, Wang, Yifan, Francois, Marc, Rezgui, Houssem, Lucas, Reveil, Maneux, Cristell

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Architecture and Finite Precision Optimization for Layered LDPC Decoders by Marchand, Cédric, Conde-Canencia, Laura, Boutillon, Emmanuel

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Design, Evaluation, and Optimization of Physical Unclonable Functions Based on Transient Effect Ring Oscillators by Cherkaoui, Abdelkarim, Bossuet, Lilian, Marchand, Cedric

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3-D Logic Circuit Design-Oriented Electrothermal Modeling of Vertical Junctionless Nanowire FETs by Mannaa, Sara, Poittevin, Arnaud, Marchand, Cédric, Deleruyelle, Damien, Deveautour, Bastien, Bosio, Alberto, O’Connor, Ian, Mukherjee, Chhandak, Wang, Yifan, Rezgui, Houssem, Deng, Marina, Maneux, Cristell, Müller, Jonas, Pelloquin, Sylvain, Moustakas, Konstantinos, Larrieu, Guilhem

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VNWFET-Based Technology: From Device Modelling to Standard Cell Library by Mannaa, Sara, Marchand, Cedric, Deleruyelle, Damien, Deveautour, Bastien, O'Connor, Ian, Bosio, Alberto

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3D Logic circuit design oriented electrothermal modeling of vertical junctionless nanowire FETs by Mannaa, Sara, Poittevin, Arnaud, Marchand, Cedric, Deleruyelle, Damien, Deveautour, Bastien, Bosio, Alberto, O'Connor, Ian, Mukherjee, Chhandak, Wang, Yifan, Rezgui, Houssem, Deng, Marina, Maneux, Cristell, Muller, Jonas, Pelloquin, Sylvain, Moustakas, Konstantinos, Larrieu, Guilhem

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Before convergence early stopping criterion for inner LDPC code in DVB standards by Marchand, C, Boutillon, E

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Hardware Emulation of FeFET On FPGA by Paul-Antoine, Matrangolo, Cedric, Marchand, David, Navarro, O'Connor, Ian

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A FeFET-Based Hybrid Memory Accessible by Content and by Address by Marchand, Cedric, O'Connor, Ian, Cantan, Mayeul, Breyer, Evelyn T., Slesazeck, Stefan, Mikolajick, Thomas

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Emerging Technologies: Challenges and Opportunities for Logic Synthesis by Bosio, Alberto, Cantan, Mayeul, Marchand, Cedric, O'Connor, Ian, Fiser, Petr, Poittevin, Arnaud, Traiola, Marcello

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