Search Results - Martins, Mayler

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  1. 1
    From Virtual Characterization to Test-Chips: DFM Analysis Through Pattern Enumeration

    From Virtual Characterization to Test-Chips: DFM Analysis Through Pattern Enumeration by Martins, Mayler G. A., Pagliarini, Samuel N., Isgenc, Mehmet Meric, Pileggi, Larry

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  2. 2
    Application and Product-Volume-Specific Customization of BEOL Metal Pitch

    Application and Product-Volume-Specific Customization of BEOL Metal Pitch by Pagliarini, Samuel N., Isgenc, Mehmet Meric, Martins, Mayler G. A., Pileggi, Lawrence

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  3. 3
    Logic IP for Low-Cost IC Design in Advanced CMOS Nodes

    Logic IP for Low-Cost IC Design in Advanced CMOS Nodes by Isgenc, Mehmet Meric, Martins, Mayler G. A., Zackriya, V. Mohammed, Pagliarini, Samuel N., Pileggi, Larry

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  4. 4
    A Simple and Effective Heuristic Method for Threshold Logic Identification

    A Simple and Effective Heuristic Method for Threshold Logic Identification by Neutzling, Augusto, Martins, Mayler G. A., Callegaro, Vinicius, Reis, Andre I., Ribas, Renato P.

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  5. 5
    Exploring the use of approximate TMR to mask transient faults in logic with low area overhead

    Exploring the use of approximate TMR to mask transient faults in logic with low area overhead by Gomes, Iuri A.C., Martins, Mayler G.A., Reis, André I., Kastensmidt, Fernanda Lima

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  6. 6
    Factored Forms for Memristive Material Implication Stateful Logic

    Factored Forms for Memristive Material Implication Stateful Logic by Marranghello, Felipe S., Callegaro, Vinicius, Martins, Mayler G. A., Reis, Andre I., Ribas, Renato P.

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  7. 7
    Evaluating Architectural, Redundancy, and Implementation Strategies for Radiation Hardening of FinFET Integrated Circuits

    Evaluating Architectural, Redundancy, and Implementation Strategies for Radiation Hardening of FinFET Integrated Circuits by Pagliarini, Samuel, Benites, Luis, Martins, Mayler, Rech, Paolo, Kastensmidt, Fernanda

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  8. 8
    Improved logic synthesis for memristive stateful logic using multi-memristor implication

    Improved logic synthesis for memristive stateful logic using multi-memristor implication by Marranghello, Felipe S., Callegaro, Vinicius, Martins, Mayler G. A., Reis, Andre I., Ribas, Renato P.

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  9. 9
    A Security-aware and LUT-based CAD Flow for the Physical Synthesis of hASICs

    A Security-aware and LUT-based CAD Flow for the Physical Synthesis of hASICs by Abideen, Zain Ul, Perez, Tiago Diadami, Martins, Mayler, Pagliarini, Samuel

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  10. 10
    A constructive approach for threshold logic circuit synthesis

    A constructive approach for threshold logic circuit synthesis by Neutzling, Augusto, Martins, Mayler G. A., Ribas, Renato P., Reis, Andre I.

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  11. 11
    Boolean factoring with multi-objective goals

    Boolean factoring with multi-objective goals by Martins, M G A, Rosa, L, Rasmussen, A B, Ribas, R P, Reis, A I

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  12. 12
    Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible?

    Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible? by Moreira, Matheus, Neutzling, Augusto, Martins, Mayler, Reis, André, Ribas, Renato, Calazans, Ney

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  13. 13
    Majority-based logic synthesis for nanometric technologies

    Majority-based logic synthesis for nanometric technologies by Martins, Mayler G. A., Callegaro, Vinicius, Marranghello, Felipe S., Ribas, Renato P., Reis, Andre I.

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  14. 14
    Iterative remapping respecting timing constraints

    Iterative remapping respecting timing constraints by Machado, Lucas, Martins, Mayler G. A., Callegaro, Vinicius, Ribas, Renato P., Reis, Andre I.

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  15. 15
    Exploring factored forms for sequential implication logic synthesis

    Exploring factored forms for sequential implication logic synthesis by Marranghello, Felipe S., Martins, Mayler G. A., Callegaro, Vinicius, Reis, Andre I., Ribas, Renato P.

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  16. 16
    Functional composition: A new paradigm for performing logic synthesis

    Functional composition: A new paradigm for performing logic synthesis by Martins, M. G. A., Ribas, R. P., Reis, A. I.

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  17. 17
    Modeling of ZnS quantum dots synthesis by DFT techniques

    Modeling of ZnS quantum dots synthesis by DFT techniques by de Queiroz, Alvaro A.A., Martins, Mayler, Soares, Demétrio A.W., França, Écio J.

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  18. 18
    Virtual characterization for exhaustive DFM evaluation of logic cell libraries

    Virtual characterization for exhaustive DFM evaluation of logic cell libraries by Pagliarini, Samuel, Martins, Mayler, Pileggi, Lawrence

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  19. 19
    Novel Solid State Nitric Oxide Sensor Using Siloxane-Poly(Oxypropylene) (PPO)

    Novel Solid State Nitric Oxide Sensor Using Siloxane-Poly(Oxypropylene) (PPO) by Herculano, Rondinelli D., Brunello, Carlos A., Melo Jr, Jair P., Martins, Mayler, Borges, Felipe A., Chiavacci, Leila A., Graeff, Carlos F. O.

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  20. 20
    A Security-aware and LUT-based CAD Flow for the Physical Synthesis of eASICs

    A Security-aware and LUT-based CAD Flow for the Physical Synthesis of eASICs by Zain UlAbideen, Perez, Tiago Diadami, Martins, Mayler, Pagliarini, Samuel

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