SPICE modeling and quick estimation of MOSFET mismatch based on BSIM3 model and parametric tests by Zhang, Q., Liou, J.J., McMacken, J.R., Thomson, J., Layman, P.

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Modeling the effect of phosphorus dose loss at the SiO/sub 2/ interface on CMOS device characteristics by Vuong, H.-H., Rafferty, C.S., McMacken, J.R., Ning, J., Chaudhry, S.

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Modeling C-V shifts in boron/BF/sub 2/-implanted capacitors by Vuong, H.-H., Rafferty, C.S., Mansfield, W., Luftman, H., Jacobson, D., Pinto, M.R., Eshraghi, S.A., McMacken, J.R., Ham, T.E.

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Multiple gate oxide thickness for 2 GHz system-on-a-chip technologies by Liu, C.T., Ma, Y., Oh, M., Diodato, P.W., Stiles, K.R., Mcmacken, J.R., Li, F., Chang, C.P., Cheung, K.P., Colonell, J.I., Lai, W.Y.C., Liu, R., Lloyd, E.J., Miner, J.F., Pai, C.S., Vaidya, H., Frackoviak, J., Timko, A., Klemens, F., Maynard, H., Clemens, J.T.

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Statistical modeling of MOS devices based on parametric test data for improved IC manufacturing by Liou, J.J., Qiang Zhang, McMacken, J., Thomson, J.R., Stiles, K., Layman, P.

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