On the data model and access method of summary data management by Chen, M.C., McNamee, L.P.

Get full text

Extracting Schematic-Like Information from CMOS Circuit Net-Lists by Wen-Jeng Lue, McNamee, L.P.

Request full text

Photogrammetric calibration of a mobile robot model by McNamee, L.P., Petrin, E.M., Spoelder, H.J.W.

Request full text

Structure optimization in logic schematic generation by Lee, T.D., McNamee, L.P.

Request full text

The Qualified Function Approach to Analysis of Program Behavior and Performance by Gabrielian, A., McNamee, L.P., Trawick, D.J.

Get full text

PLAY: pattern-based symbolic cell layout: Part I: transistor placement by Lue, W.-J., McNamee, L. P.

Request full text

VISION: VHDL induced schematic imaging on net-lists by Chun, R. K., Chang, K.-J., McNamee, L. P.

Request full text

A simple method for determining static parameters of large signal semiconductor diode and transistor models by Zaniolo, C., McNamee, L.P.

Get full text

Iterative Solution of Large-Scale Systems by Hybrid Techniques by Wei Chen, McNamee, L.P.

Get full text

A graph-based signal flow direction assignment method for CMOS circuits by Wang, P.-H.P., McNamee, L.P.

Request full text

A means of reducing custom LSI interconnection requirements by Calhoun, D.F., McNamee, L.P.

Get full text

Symbolic Parasitic Extractor for Circuit Simulation (SPECS) by Bastian, J.D., Ellement, M., Fowler, P.J., Huang, C.E., McNamee, L.P.

Request full text

Identification of Disjunctively Decomposable Logic Functions Employing a Karnaugh Map by Kermani, M.B., Mickle, M.H., McNamee, L.P.

Get full text