A symmetric 0.25 /spl mu/m CMOS technology for low-power, high-performance ASIC applications using 248 nm DUV lithography by Boulin, D.M., Mansfield, W.M., O'Connor, K.J., Bevk, J., Brasen, D., Cheng, M., Cirelli, R.A., Eshraghi, S.A., Green, M.L., Guinn, K.V., Hillenius, S.J., Ibbotson, D.E., Jacobson, D.C., Kim, Y.O., King, C.A., Kistler, R.C., Klemens, F.P., Krisch, K.S., Kornblit, A., Lee, J.T.C., Manchanda, L., McNevin, S.C., Moccio, S.V., Monroe, D.P., Ng, K.K., O'Malley, M.L., Rafferty, C.S., Schwartz, G.P., Vaidya, S., Weber, G.R., Feldman, L.C., Pinto, M.R., Itani, T., Tounai, T., Kasama, K., Miyamoto, H., Ikawa, E., Hasagawa, E., Ishitani, A., Ito, H., Horiuchi, T., Saito, S., Nakamae, M.

Request full text