Search Results - Mehendale, Mahesh

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  1. 1
    Memory Bandwidth and Power Reduction Using Lossy Reference Frame Compression in Video Encoding

    Memory Bandwidth and Power Reduction Using Lossy Reference Frame Compression in Video Encoding by Gupte, A D, Amrutur, B, Mehendale, M M, Rao, A V, Budagavi, M

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  2. 2
    An area-efficient 6T-SRAM based Compute-In-Memory architecture with reconfigurable SAR ADCs for energy-efficient deep neural networks in edge ML applications

    An area-efficient 6T-SRAM based Compute-In-Memory architecture with reconfigurable SAR ADCs for energy-efficient deep neural networks in edge ML applications by Biswas, Avishek, Sanghvi, Hetul, Mehendale, Mahesh, Preet, G

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  3. 3
    RAMAN: A Reconfigurable and Sparse tinyML Accelerator for Inference on Edge

    RAMAN: A Reconfigurable and Sparse tinyML Accelerator for Inference on Edge by Krishna, Adithya, Rohit Nudurupati, Srikanth, Chandana, D. G., Dwivedi, Pritesh, van Schaik, Andre, Mehendale, Mahesh, Thakur, Chetan Singh

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  4. 4
    Bi-Modal DRAM Cache: Improving Hit Rate, Hit Latency and Bandwidth

    Bi-Modal DRAM Cache: Improving Hit Rate, Hit Latency and Bandwidth by Gulur, Nagendra, Mehendale, Mahesh, Manikantan, R., Govindarajan, R.

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  5. 5
    Live Demonstration: Real-time audio and visual inference on the RAMAN TinyML accelerator

    Live Demonstration: Real-time audio and visual inference on the RAMAN TinyML accelerator by Krishna, Adithya, Rajesh, Ashwin, Oleti, Hitesh Pavan, Chauhan, Anand, H, Shankaranarayanan, Van Schaik, Andre, Mehendale, Mahesh, Thakur, Chetan Singh

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  6. 6
    150nA IQ, Quad Input - Quad Output, Intelligent Integrated Power Management for IoT Applications

    150nA IQ, Quad Input - Quad Output, Intelligent Integrated Power Management for IoT Applications by Singhal, Vipul, Chauhan, Rajat, Menezes, Vinod, Manikandan, RR, Magod, Raveesh, Mehendale, Mahesh, Chandrakasan, Anantha

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  7. 7
    A 1.2 pJ/cycle KHz Timer Circuit for Heavily Duty-Cycled Systems

    A 1.2 pJ/cycle KHz Timer Circuit for Heavily Duty-Cycled Systems by Manikandan, R.R., Singhal, Vipul, Chauhan, Rajat, Menezes, Vinod, Mehendale, Mahesh

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  8. 8
    8.3 A 10.5μA/MHz at 16MHz single-cycle non-volatile memory access microcontroller with full state retention at 108nA in a 90nm process

    8.3 A 10.5μA/MHz at 16MHz single-cycle non-volatile memory access microcontroller with full state retention at 108nA in a 90nm process by Singhal, Vipul Kumar, Menezes, Vinod, Chakravarthy, Srinivasa, Mehendale, Mahesh

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  9. 9
    F1: Designing secure systems: Manufacturing, circuits and architectures

    F1: Designing secure systems: Manufacturing, circuits and architectures by De, Vivek, Bernstein, Kerry, Yoshikawa, Takefumi, Leblebici, Yusuf, Verhelst, Marian, Mehendale, Mahesh, Nagata, Makoto

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  10. 10
    A true multistandard, programmable, low-power, full HD video-codec engine for smartphone SoC

    A true multistandard, programmable, low-power, full HD video-codec engine for smartphone SoC by Mehendale, M., Das, S., Sharma, M., Mody, M., Reddy, R., Meehan, J., Tamama, H., Carlson, B., Polley, M.

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  11. 11
    A 28nm programmable and low power ultra-HD video codec engine

    A 28nm programmable and low power ultra-HD video codec engine by Sanghvi, Hetul, Mody, Mihir, Nandan, Niraj, Mehendale, Mahesh, Das, Subrangshu, Mandal, Dipan Kumar, Shastry, Pavan

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  12. 12
    Accelerating H.264/HEVC video slice processing using application specific instruction set processor

    Accelerating H.264/HEVC video slice processing using application specific instruction set processor by Mandal, Dipan Kumar, Mody, Mihir, Mehendale, Mahesh, Yadav, Naresh, Chaitanya, Ghone, Goswami, Piyali, Sanghvi, Hetul, Nandan, Niraj

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  13. 13
    A monolithic programmable Ultra-HD video codec engine

    A monolithic programmable Ultra-HD video codec engine by Sanghvi, Hetul, Mody, Mihir, Nandan, Niraj, Mehendale, Mahesh, Das, Subrangshu, Mandal, Dipan Kumar, Nainala, Vyagrheswarudu, Baireddy, Vijayavardhan, Shastry, Pavan

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  14. 14
    Row-Buffer Reorganization: Simultaneously Improving Performance and Reducing Energy in DRAMs

    Row-Buffer Reorganization: Simultaneously Improving Performance and Reducing Energy in DRAMs by Gulur, N., Manikantan, R., Govindarajan, R., Mehendale, M.

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  15. 15
    TinyML Acoustic Classification using RAMAN Accelerator and Neuromorphic Cochlea

    TinyML Acoustic Classification using RAMAN Accelerator and Neuromorphic Cochlea by Krishna, Adithya, Shankaranarayanan, H, Oleti, Hitesh Pavan, Chauhan, Anand, van Schaik, Andre, Mehendale, Mahesh, Thakur, Chetan Singh

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  16. 16
    Plenary talks - 11 abstracts

    Plenary talks - 11 abstracts by Borkar, Shekhar, Kopetz, Herman, Iwai, Hiroshi, Fujita, Masahiro, Nandy, S. K., Wei Zhao, Taneja, Sanjiv, Rajski, Janusz, Zebo Peng, Mitra, Subhasish, Mehendale, Mahesh

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  17. 17
    ANATOMY: an analytical model of memory system performance

    ANATOMY: an analytical model of memory system performance by Gulur, Nagendra, Mehendale, Mahesh, Manikantan, Raman, Govindarajan, Ramaswamy

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  18. 18
    Low-power realization of FIR filters on programmable DSPs

    Low-power realization of FIR filters on programmable DSPs by Mehendale, M., Sherlekar, S.D., Venkatesh, G.

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  19. 19
    RAMAN: A Re-configurable and Sparse tinyML Accelerator for Inference on Edge

    RAMAN: A Re-configurable and Sparse tinyML Accelerator for Inference on Edge by Adithya Krishna, Srikanth Rohit Nudurupati, Chandana, D G, Dwivedi, Pritesh, André van Schaik, Mehendale, Mahesh, Chetan Singh Thakur

    Published in arXiv.org
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  20. 20
    DBQ: A Differentiable Branch Quantizer for Lightweight Deep Neural Networks

    DBQ: A Differentiable Branch Quantizer for Lightweight Deep Neural Networks by Dbouk, Hassan, Sanghvi, Hetul, Mehendale, Mahesh, Shanbhag, Naresh

    Published in arXiv.org
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