Search Results - Menon, P.R.

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  1. 1
    Design-specific path delay testing in lookup-table-based FPGAs

    Design-specific path delay testing in lookup-table-based FPGAs by Menon, P.R., Weifeng Xu, Tessier, R.

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  2. 2
    Identification of primitive faults in combinational and sequential circuits

    Identification of primitive faults in combinational and sequential circuits by Tekumalla, R.C., Menon, P.R.

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  3. 3
    BIST-based delay path testing in FPGA architectures

    BIST-based delay path testing in FPGA architectures by Harris, I.G., Menon, P.R., Tessier, R.

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  4. 4
    Modelling of Gangotri glacier thickness and volume using an artificial neural network

    Modelling of Gangotri glacier thickness and volume using an artificial neural network by Haq, Mohd Anul, Jain, Kamal, Menon, K.P.R.

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  5. 5
    On redundant path delay faults in synchronous sequential circuits

    On redundant path delay faults in synchronous sequential circuits by Tekumalla, R.C., Menon, P.R.

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  6. 6
    Preparation and characterization of iron aluminide based intermetallic alloy from titaniferous magnetite ore

    Preparation and characterization of iron aluminide based intermetallic alloy from titaniferous magnetite ore by Chakraborty, S.P., Sharma, I.G., Menon, P.R., Suri, A.K.

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  7. 7
    Logic optimization and equivalence checking by implication analysis

    Logic optimization and equivalence checking by implication analysis by Kunz, W., Stoffel, D., Menon, P.R.

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  8. 8
    Synthesis of delay-verifiable combinational circuits

    Synthesis of delay-verifiable combinational circuits by Ke, W., Menon, P.R.

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  9. 9
    Delay testing with clock control: an alternative to enhanced scan

    Delay testing with clock control: an alternative to enhanced scan by Tekumalla, R.C., Menon, P.R.

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  10. 10
    Delay-testable implementations of symmetric functions

    Delay-testable implementations of symmetric functions by Ke, W., Menon, P.R.

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  11. 11
    Multifault testability of delay-testable circuits

    Multifault testability of delay-testable circuits by Ke, W., Menon, P.R.

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  12. 12
    Characterization of water vapor permeation through thin film Parylene C

    Characterization of water vapor permeation through thin film Parylene C by Menon, P.R., Li, W., Tooker, A., Tai, Y.C.

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  13. 13
    Robust testability of primitive faults using test points

    Robust testability of primitive faults using test points by Tekumalla, R.C., Menon, P.R.

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  14. 14
    Path-delay-fault testable nonscan sequential circuits

    Path-delay-fault testable nonscan sequential circuits by Wuudiann Ke, Menon, P.R.

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  15. 15
    Redundancy identification and removal in combinational circuits

    Redundancy identification and removal in combinational circuits by Menon, P.R., Ahuja, H., Harihara, M.

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  16. 16
    Identifying redundant path delay faults in sequential circuits

    Identifying redundant path delay faults in sequential circuits by Tekumalla, R., Menon, P.R.

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  17. 17
    Stuck-open testable scan-based CMOS sequential circuits

    Stuck-open testable scan-based CMOS sequential circuits by Park, B.-H., Menon, P.R.

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  18. 18
    3-valued trace-based fault simulation of synchronous sequential circuits

    3-valued trace-based fault simulation of synchronous sequential circuits by Song, O.Y., Menon, P.R.

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  19. 19
    Acceleration of trace-based fault simulation of combinational circuits

    Acceleration of trace-based fault simulation of combinational circuits by Song, O.Y., Menon, P.R.

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  20. 20
    Synthesis of delay verifiable sequential circuits using partial enhanced scan

    Synthesis of delay verifiable sequential circuits using partial enhanced scan by Takumalla, R.C., Menon, P.R.

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