Search Results - Mesgarzadeh, B.

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  1. 1
    A Low-Power Digital DLL-Based Clock Generator in Open-Loop Mode

    A Low-Power Digital DLL-Based Clock Generator in Open-Loop Mode by Mesgarzadeh, B., Alvandpour, A.

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  2. 2
    Jitter Characteristic in Charge Recovery Resonant Clock Distribution

    Jitter Characteristic in Charge Recovery Resonant Clock Distribution by Mesgarzadeh, B., Hansson, M., Alvandpour, A.

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  3. 3
    A study of injection locking in ring oscillators

    A study of injection locking in ring oscillators by Mesgarzadeh, B., Alvandpour, A.

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  4. 4
    Heterogeneity among melanoma databases and challenges in sustainability: A survey of the Melanoma Prevention Working Group

    Heterogeneity among melanoma databases and challenges in sustainability: A survey of the Melanoma Prevention Working Group by Mesgarzadeh, Sheyda, Myrdal, Caitlyn N., Gong, Amanda H., Stratton, Delaney B., Kelly, Brenna G., Curiel-Lewandrowski, Clara

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  5. 5
    A DLL-based injection-locked frequency synthesizer for WiMedia UWB

    A DLL-based injection-locked frequency synthesizer for WiMedia UWB by Ojani, A., Mesgarzadeh, B., Alvandpour, A.

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  6. 6
    Coalescing plaques on the face, trunk, and upper extremities

    Coalescing plaques on the face, trunk, and upper extremities by Myrdal, Caitlyn N., Mesgarzadeh, Sheyda, Loh, Tiffany Y., Culpepper, Keliegh S., Curiel-Lewandrowski, Clara

    Published in JAAD Case Reports
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  7. 7
    A process variation tolerant DLL-based UWB frequency synthesizer

    A process variation tolerant DLL-based UWB frequency synthesizer by Ojani, A., Mesgarzadeh, B., Alvandpour, A.

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  8. 8
    EMI reduction by resonant clock distribution networks

    EMI reduction by resonant clock distribution networks by Mesgarzadeh, B, Alvandpour, A

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  9. 9
    A Class-D stage with harmonic suppression and DLL-based phase generation

    A Class-D stage with harmonic suppression and DLL-based phase generation by Fritzin, J., Mesgarzadeh, B., Alvandpour, A.

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  10. 10
    First-Harmonic Injection-Locked Ring Oscillators

    First-Harmonic Injection-Locked Ring Oscillators by Mesgarzadeh, B., Alvandpour, A.

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  11. 11
    Low-power bufferless resonant clock distribution networks

    Low-power bufferless resonant clock distribution networks by Mesgarzadeh, B., Hansson, M., Alvandpour, A.

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  12. 12
    1.56 GHz On-chip Resonant Clocking in 130nm CMOS

    1.56 GHz On-chip Resonant Clocking in 130nm CMOS by Hansson, M., Mesgarzadeh, B., Alvandpour, A.

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  13. 13
    A 2-GHz 7-mW digital DLL-based frequency multiplier in 90-nm CMOS

    A 2-GHz 7-mW digital DLL-based frequency multiplier in 90-nm CMOS by Mesgarzadeh, B., Alvandpour, A.

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  14. 14
    A wide-tuning range 1.8 GHz quadrature VCO utilizing coupled ring oscillators

    A wide-tuning range 1.8 GHz quadrature VCO utilizing coupled ring oscillators by Mesgarzadeh, B., Alvandpour, A.

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  15. 15
    Jitter Characteristic in Resonant Clock Distribution

    Jitter Characteristic in Resonant Clock Distribution by Mesgarzadeh, B., Hansson, M., Alvandpour, A.

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  16. 16
    Synchronous latency-insensitive design for multiple clock domain

    Synchronous latency-insensitive design for multiple clock domain by Edman, A., Svensson, C., Mesgarzadeh, B.

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  17. 17
    A 16 GSPS 0.18 μm CMOS decimator for single-bit Σ Δ-modulation

    A 16 GSPS 0.18 μm CMOS decimator for single-bit Σ Δ-modulation by Ohlsson, H., Mesgarzadeh, B., Johansson, K., Gustafsson, O., Lowenborg, P., Johansson, H., Alvandpour, A.

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  18. 18
    Reliability challenges in avionics due to silicon aging

    Reliability challenges in avionics due to silicon aging by Mesgarzadeh, B., Soderquist, I., Alvandpour, A.

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  19. 19
    A CMOS implementation of current-mode min-max circuits and a sample fuzzy application

    A CMOS implementation of current-mode min-max circuits and a sample fuzzy application by Mesgarzadeh, B.

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  20. 20
    A multi-segment clocking scheme to reduce on-chip EMI

    A multi-segment clocking scheme to reduce on-chip EMI by Mesgarzadeh, B., Zadeh, I. E., Alvandpour, A.

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