Search Results - Meswani, Mitesh

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  1. 1
    Heterogeneous memory architectures: A HW/SW approach for mixing die-stacked and off-package memories

    Heterogeneous memory architectures: A HW/SW approach for mixing die-stacked and off-package memories by Meswani, Mitesh R., Blagodurov, Sergey, Roberts, David, Slice, John, Ignatowski, Mike, Loh, Gabriel H.

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  2. 2
    Modeling and predicting performance of high performance computing applications on hardware accelerators

    Modeling and predicting performance of high performance computing applications on hardware accelerators by Meswani, Mitesh R., Carrington, Laura, Unat, Didem, Snavely, Allan, Baden, Scott, Poole, Stephen

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  3. 3
    MemPod: A Clustered Architecture for Efficient and Scalable Migration in Flat Address Space Multi-level Memories

    MemPod: A Clustered Architecture for Efficient and Scalable Migration in Flat Address Space Multi-level Memories by Prodromou, Andreas, Meswani, Mitesh, Jayasena, Nuwan, Loh, Gabriel, Tullsen, Dean M.

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  4. 4
    Design and Analysis of an APU for Exascale Computing

    Design and Analysis of an APU for Exascale Computing by Vijayaraghavan, Thiruvengadam, Karunanithi, Arun, Kayiran, Onur, Meswani, Mitesh, Paul, Indrani, Poremba, Matthew, Raasch, Steven, Reinhardt, Steven K., Sadowski, Greg, Sridharan, Vilas, Eckert, Yasuko, Loh, Gabriel H., Schulte, Michael J., Ignatowski, Mike, Beckmann, Bradford M., Brantley, William C., Greathouse, Joseph L., Huang, Wei

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  5. 5
    SILC-FM: Subblocked InterLeaved Cache-Like Flat Memory Organization

    SILC-FM: Subblocked InterLeaved Cache-Like Flat Memory Organization by Jee Ho Ryoo, Meswani, Mitesh R., Prodromou, Andreas, John, Lizy K.

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  6. 6
    Modeling and predicting performance of high performance computing applications on hardware accelerators : Applications for the Heterogeneous Computing Era

    Modeling and predicting performance of high performance computing applications on hardware accelerators : Applications for the Heterogeneous Computing Era by MESWANI, Mitesh R, CARRINGTON, Laura, UNAT, Didem, SNAVELY, Allan, BADEN, Scott, POOLE, Stephen

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  7. 7
    PIR: PMaC's Idiom Recognizer

    PIR: PMaC's Idiom Recognizer by Olschanowsky, C, Snavely, A, Meswani, M R, Carrington, L

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  8. 8
    Modeling and Predicting Performance of High Performance Computing Applications on Hardware Accelerators

    Modeling and Predicting Performance of High Performance Computing Applications on Hardware Accelerators by Meswani, M. R., Carrington, L., Unat, D., Snavely, A., Baden, S., Poole, S.

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  9. 9
    Modeling and Predicting Disk I/O Time of HPC Applications

    Modeling and Predicting Disk I/O Time of HPC Applications by Meswani, M. R., Laurenzano, M. A., Carrington, L., Snavely, A.

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  10. 10
    Modeling and predicting application performance on hardware accelerators

    Modeling and predicting application performance on hardware accelerators by Meswani, M. R., Carrington, L., Unat, D., Snavely, A., Baden, S., Poole, S.

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  11. 11
    Predicting disk I/O time of HPC applications on flash drives

    Predicting disk I/O time of HPC applications on flash drives by Meswani, M R, Cicotti, P, Jiahua He, Snavely, A

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  12. 12
    A Study of the Influence of the POWER5 Dynamic Resource Balancing (DRB) on Optimal Hardware Thread Priorities

    A Study of the Influence of the POWER5 Dynamic Resource Balancing (DRB) on Optimal Hardware Thread Priorities by Trillo, Princess C, Meswani, Mitesh R, Teller, Patricia J, Arunagiri, Sarala

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