Search Results - Miyase, K

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  1. 1
    XID: Don't care identification of test patterns for combinational circuits

    XID: Don't care identification of test patterns for combinational circuits by Miyase, K., Kajihara, S.

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  2. 2
    Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch

    Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch by Asada, K., Wen, X., Holst, S., Miyase, K., Kajihara, S., Kochte, M. A., Schneider, E., Wunderlich, H.-J, Qian, J.

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  3. 3
    Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment

    Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment by Meng-Fan Wu, Jiun-Lang Huang, Xiaoqing Wen, Miyase, K.

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  4. 4
    Power-aware test generation with guaranteed launch safety for at-speed scan testing

    Power-aware test generation with guaranteed launch safety for at-speed scan testing by Wen, X, Enokimoto, K, Miyase, K, Yamato, Y, Kochte, M A, Kajihara, S, Girard, P, Tehranipoor, M

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  5. 5
    On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression

    On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression by Enokimoto, K., Xiaoqing Wen, Miyase, K., Jiun-Lang Huang, Kajihara, S., Laung-Terng Wang

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  6. 6
    On pinpoint capture power management in at-speed scan test generation

    On pinpoint capture power management in at-speed scan test generation by Wen, X., Nishida, Y., Miyase, K., Kajihara, S., Girard, P., Tehranipoor, M., Wang, L-T

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  7. 7
    CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing

    CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing by Furukawa, H., Wen, X., Miyase, K., Yamato, Y., Kajihara, S., Girard, P., Wang, L.-T., Tehranipoor, M.

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  8. 8
    Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling

    Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling by Miyase, K., Uchinodan, Y., Enokimoto, K., Yamato, Y., Wen, X., Kajihara, S., Wu, F., Dilillo, L., Bosio, A., Girard, P., Virazel, A.

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  9. 9
    CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing

    CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing by Enokimoto, K., Wen, X., Yamato, Y., Miyase, K., Sone, H., Kajihara, S., Aso, M., Furukawa, H.

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  10. 10
    Optimal scan tree construction with test vector modification for test compression

    Optimal scan tree construction with test vector modification for test compression by Miyase, Kajihara

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  11. 11
    Test vector modification for power reduction during scan testing

    Test vector modification for power reduction during scan testing by Kajihara, S., Ishida, K., Miyase, K.

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  12. 12
    On test data volume reduction for multiple scan chain designs

    On test data volume reduction for multiple scan chain designs by Reddy, S.M., Miyase, K., Kajihara, S., Pomeranz, I.

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  13. 13
    Is test power reduction through X-filling good enough?

    Is test power reduction through X-filling good enough? by Wu, F, Dilillo, L, Bosio, A, Girard, P, Pravossoudovitch, S, Virazel, A, Tehranipoor, M, Miyase, K, Wen, X, Ahmed, N

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  14. 14
    Multiple scan tree design with test vector modification

    Multiple scan tree design with test vector modification by Miyase, K., Kajihara, S., Reddy, S.M.

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  15. 15
    On Improving Defect Coverage of Stuck-at Fault Tests

    On Improving Defect Coverage of Stuck-at Fault Tests by Miyase, K., Terashima, K., Kajihara, S., Wen, X., Reddy, S.M.

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  16. 16
    Don't-care identification on specific bits of test patterns

    Don't-care identification on specific bits of test patterns by Miyase, K., Kajihara, S., Pomeranz, I., Reddy, S.M.

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  17. 17
    Low Power BIST for Scan-Shift and Capture Power

    Low Power BIST for Scan-Shift and Capture Power by Sato, Y., Senling Wang, Kato, T., Miyase, K., Kajihara, S.

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  18. 18
    On identifying don't care inputs of test patterns for combinational circuits

    On identifying don't care inputs of test patterns for combinational circuits by Kajihara, S., Miyase, K.

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  19. 19
    Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Scan Testing

    Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Scan Testing by Meng-Fan Wu, Jiun-Lang Huang, Xiaoqing Wen, Miyase, K.

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  20. 20
    A novel scheme to reduce power supply noise for high-quality at-speed scan testing

    A novel scheme to reduce power supply noise for high-quality at-speed scan testing by Xiaoqing Wen, Miyase, K., Kajihara, S., Suzuki, T., Yamato, Y., Girard, P., Ohsumi, Y., Laung-Terng Wang

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