Downscaling limit of equivalent oxide thickness in formation of ultrathin gate dielectric by thermal-enhanced remote plasma nitridation by Chen, Chien-Hao, Fang, Yean-Kuen, Ting, Shyh-Fann, Hsieh, Wen-Tse, Yang, Chih-Wei, Hsu, Tzu-Hsuan, Yu, Mo-Chiun, Lee, Tze-Liang, Chen, Shih-Chang, Yu, Chen-Hua, Liang, Mong-Song

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Edge hole direct tunneling leakage in ultrathin gate oxide p-channel MOSFETs by Kuo-Nan Yang, Huan-Tsung Huang, Ming-Jer Chen, Yeou-Ming Lin, Mo-Chiun Yu, Jang, S.S.A., Yu, D.C.H., Mong-Song Liang

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Reliable tantalum-gate fully-depleted-SOI MOSFET technology featuring low-temperature processing by Ushiki, T., Mo-Chiun Yu, Hirano, Y., Shimada, H., Morita, M., Ohmi, T.

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To optimize electrical properties of the ultrathin (1.6 nm) nitride/oxide gate stacks with bottom oxide materials and post-deposition treatment by Chein-Hao Chen, Yean-Kuen Fang, Chih-Wei Yang, Shyh-Fann Ting, Yong-Shiuan Tsair, Ming-Fang Wang, Tuo-Hong Hou, Mo-Chiun Yu, Shih-Chang Chen, Jang, S.M., Yu, D.C.H., Mong-Song Liang

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Improvement of gate oxide reliability for tantalum-gate MOS devices using xenon plasma sputtering technology by Ushiki, T., Kawai, K., Mo-Chiun Yu, Shinohara, T., Ino, K., Morita, M., Ohmi, T.

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Gate oxide reliability concerns in gate-metal sputtering deposition process: an effect of low-energy large-mass ion bombardment by Ushiki, Takeo, Yu, Mo-Chiun, Kawai, Kunihiro, Shinohara, Toshikuni, Ino, Kazuhide, Morita, Mizuho, Ohmi, Tadahiro

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A physical model for hole direct tunneling current in p+ poly-gate pMOSFETs with ultrathin gate oxides by Yang, Kuo-Nan, Huang, Huan-Tsung, Chang, Ming-Chin, Chu, Che-Min, Chen, Yuh-Shu, Chen, Ming-Jer, Lin, Yeou-Ming, Yu, Mo-Chiun, Jang, S M, Yu, C H, Liang, M S

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A physical model for hole direct tunneling current in p/sup +/ poly-gate pMOSFETs with ultrathin gate oxides by Kuo-Nan Yang, Huan-Tsung Huang, Ming-Chin Chang, Che-Min Chu, Yuh-Shu Chen, Ming-Jer Chen, Yeou-Ming Lin, Mo-Chiun Yu, Jang, S.M., Yu, C.H., Liang, M.S.

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Physical model for hole direct tunneling current in P super(+) poly-gate PMOSFETs with ultrathin gate oxides by Yang, Kuo-Nan, Huang, Huan-Tsung, Chang, Ming-Chin, Chu, Che-Min, Chen, Yuh-Shu, Chen, Ming-Jer, Lin, Yeou-Ming, Yu, Mo-Chiun, Jang, Simon M, Yu, Douglas C H, Liang, M S

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Reliable tantalum gate fully-depleted-SOI MOSFETs with 0.15 /spl mu/m gate length by low-temperature processing below 500/spl deg/C by Ushikil, T., Mo Chiun Yu, Hirano, Y., Shimada, H., Morita, M., Ohmi, T.

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